SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide

ID 683815
Date 10/08/2021
Public

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2.8. Simulation Testbench

The simulation testbench checks for the assertion of the trs_locked signal. The testbench also detects the number of transceiver reconfiguration triggered after every video standard switching.
Figure 17. Simplex Mode Simulation Testbench Block Diagram
Figure 18. Duplex Mode Simulation Testbench Block Diagram
Table 20.  Testbench Components
Component Description
Testbench Control This block controls the test sequence of the simulation and generates the necessary stimulus signals to the TX and video pattern generator blocks.
RX Checker This checker detects the trs_locked signal from the RX protocol and compares the actual number of transceiver reconfigurations performed versus the expected number.
TX Checker This checker verifies if the TX serial data contains a valid TRS signal.
Figure 19. Sequence of Video Standards for Triple-Rate and Multi-Rate Designs
For single-rate designs, only one video standard is tested:
  • HD-SDI single-rate—HD
  • 3G-SDI single-rate—3G Level A 10-bit Multiplex
If you enable the Dynamic Tx Clock Switching parameter, only one video standard is being tested with 2 different TX PHY reference clocks to demonstrate the switching:
  • HD-SDI single-rate—HD
  • 3G-SDI single-rate/triple-rate—3G Level A 10-bit Multiplex
  • Multi-rate—12G 10-bit Multiplex Type 1
Figure 20. Simulation Waveform
A successful simulation ends with the following message:
#### TRANSMIT TEST COMPLETED SUCCESSFULLY! ####
#  
#### Channel 1: RECEIVE TEST COMPLETED SUCCESSFULLY! ####

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