- Removed NCSim from the following figure and tables:
- Figure: Directory Structure for the Design Examples.
- Table: Other Generated Files in Simulation Folder.
- Table: Steps to Run Simulation.
- Edited the list of Software in Hardware and Software Requirements:
- Changed ModelSim* - Intel® FPGA Edition to Questa*-Intel® FPGA Edition .
- Changed ModelSim* - Intel® FPGA Starter Edition to ModelSim SE* .
- Changed from Streams Interleaved to Multiplex Type to align with SMPTE spec for below:
- RX/TX/DU Top Signals Table for rx_vid_std, tx_vid_std and sdi_tx_ln_b signals.
- On-board User LED Functions Table.
- Figure Sequence of Video Standards for Triple-Rate and Multi-Rate Designs.
- Description in Simulation Testbench for single-rate and multi-rate designs.
- Updated the Directory Structure section with new folders and files for loopback design and simulation:
- Added information that the multi-rate designs support rx_coreclk frequency of 297 MHz.
- Added instructions to run simulation using the Xcelium Parallel Simulator in the Simulating the Design section.
- Edited the Hardware and Software Requirements section to include the Xcelium Parallel simulator.
- Edited the description for the tx_pll_refclk_sel signal in the Interface Signals section to include information about the dynamic switching feature.