SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide

ID 683815
Date 10/08/2021
Public

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4. Revision History for SDI II Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.10.08 21.3
  • Removed NCSim from the following figure and tables:
    • Figure: Directory Structure for the Design Examples.
    • Table: Other Generated Files in Simulation Folder.
    • Table: Steps to Run Simulation.
  • Edited the list of Software in Hardware and Software Requirements:
    • Changed ModelSim* - Intel® FPGA Edition to Questa*-Intel® FPGA Edition .
    • Changed ModelSim* - Intel® FPGA Starter Edition to ModelSim SE* .
2021.08.27 18.0
  • Changed from Streams Interleaved to Multiplex Type to align with SMPTE spec for below:
    • RX/TX/DU Top Signals Table for rx_vid_std, tx_vid_std and sdi_tx_ln_b signals.
    • On-board User LED Functions Table.
    • Figure Sequence of Video Standards for Triple-Rate and Multi-Rate Designs.
    • Description in Simulation Testbench for single-rate and multi-rate designs.
2020.01.29 18.0
  • Updated the Directory Structure section with new folders and files for loopback design and simulation:
    • modelsim_files.tcl
    • ncsim_files.tcl
    • riviera_files.tcl
    • vcs_files.tcl
    • vcsmx_files.tcl
    • xcelium_files.tcl
    • tb_ln_check.v
    • cds.lib
    • hdl.var
    • xcelium_setup.sh
    • xcelium_sim.sh
  • Added information that the multi-rate designs support rx_coreclk frequency of 297 MHz.
  • Added instructions to run simulation using the Xcelium Parallel Simulator in the Simulating the Design section.
  • Edited the Hardware and Software Requirements section to include the Xcelium Parallel simulator.
  • Edited the description for the tx_pll_refclk_sel signal in the Interface Signals section to include information about the dynamic switching feature.
2017.12.25 17.1.1 Initial release.

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