SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide

ID 683815
Date 10/08/2021
Public

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2.1. Parallel Loopback Design Examples

The parallel loopback design examples demonstrate simplex and duplex channel modes with and without external VCXO.
Note: For parallel loopback duplex designs, do not share the TX PLL reference clock with the RX transceiver reference clock. The design logic tunes the TX PLL clock to match the RX recovered clock frequency.
Figure 9. Parallel Loopback with Simplex Mode Block Diagram
Figure 10. Parallel Loopback with Simplex Mode Clocking Scheme
Figure 11. Parallel Loopback with Duplex Mode Block Diagram
Figure 12. Parallel Loopback with Duplex Mode Clocking Scheme

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