SDI II Intel® Cyclone 10 GX FPGA IP Design Example User Guide

ID 683815
Date 10/08/2021
Public

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2.6. Video Pattern Generator Parameters

Customize the video pattern generator parameters according to your design.
Table 18.   Video Pattern Generator Parameters
Parameter Valid Value Default Value Description

OUTW_MULTP

1, 4

1

Defines the width of the output ports. Select 4 for a multi-rate design, otherwise select 1.

SD_BIT_WIDTH

10, 20

10

Defines the generated SD interface bit width. This value must match with the SD interface bit width parameter of the SDI II TX core in the same design.

TEST_GEN_ANC

0, 1

0

Select 1 to generate the ancillary data packet in output stream. The module inserts the embedded Data ID (DID) packet with 10’h242 if TEST_GEN_VPID is not enabled.

TEST_GEN_VPID

0, 1

0

Select 1 to generate the payload ID packet in output streams. The module inserts the embedded Data ID (DID) packet with 10’h241.

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