AN 944: Thermal Modeling for Agilex™ 7 FPGAs with the Power and Thermal Calculator

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ID 683810
Date 6/05/2025
Public
Document Table of Contents
Document Table of Contents x
1. List of Abbreviations 2. Introduction 3. Agilex™ 7 FPGA Package Mechanical Design 4. Agilex™ 7 FPGA Thermal Design Parameters 5. Thermal Design Process for Agilex™ 7 Devices 6. Power and Thermal Calculator (PTC) for Agilex™ 7 Devices 7. Example 2—Alternative Method of Analyzing Thermal Design 8. Document Revision History for AN 944: Thermal Modeling for Agilex™ 7 FPGAs with the Power and Thermal Calculator
3. Agilex™ 7 FPGA Package Mechanical Design x
3.1. Agilex™ 7 Physical Package Structure
4. Agilex™ 7 FPGA Thermal Design Parameters x
4.1. Agilex™ 7 Compact Thermal Model (CTM) 4.2. Agilex™ 7 Temperature Sensing 4.3. Thermal Sensor Accuracy
5. Thermal Design Process for Agilex™ 7 Devices x
5.1. Thermal Parameter Dependencies and Accuracy
6. Power and Thermal Calculator (PTC) for Agilex™ 7 Devices x
6.1. Device Selection and Analysis Example 6.2. Logic Design Information 6.3. Thermal Page and Thermal Design Parameters 6.4. CTM Model 6.5. Heat Sink 6.6. CFD Model
7. Example 2—Alternative Method of Analyzing Thermal Design x
7.1. Example 2—Full Length 1 Slot PCIe with 2 FPGAs 7.2. Thermal Design Optimization
1. List of Abbreviations
2. Introduction
3. Agilex™ 7 FPGA Package Mechanical Design
4. Agilex™ 7 FPGA Thermal Design Parameters
5. Thermal Design Process for Agilex™ 7 Devices
6. Power and Thermal Calculator (PTC) for Agilex™ 7 Devices
7. Example 2—Alternative Method of Analyzing Thermal Design
8. Document Revision History for AN 944: Thermal Modeling for Agilex™ 7 FPGAs with the Power and Thermal Calculator

6.2. Logic Design Information

The Power and Thermal Calculator (PTC) has several pages for data entry.

Main Design Entry

The subject of this document is thermal analysis, therefore it focuses primarily on the thermal-related settings. For broader and more detailed information, refer to the Power and Thermal Calculator User Guide.

The following table shows settings for our PCIe board example.

Table 5.  Values for Example AGFA014R24A Agilex™ 7 Design
PTC Page Values for this Design Comment
Logic
  • 900,000 Half ALM
  • 1,800,000 FF
  • Clock: 500 MHz
  • Toggle rate: 25%
  
RAM
  • M20K
  • 5000 blocks
  • Data width: 8
  • RAM depth: 32 clock
  • Frequency: 500
  • Clock: 50%
  
DSP
  • Configuration two 18×16
  • # of instances: 4000
  • Clock: 500 MHz
  • Toggle rate: 25%
  
Clock
  • Clock: 500 MHz
  • Total fan out: 40,000
  • Global enable: 100%
  • Local enable: 100%
  
PLL
  • PLL Type: IOPLL
  • PLL block: 3
  • Output frequency: 6000 MHz
I/O
  • Application: GPIO
 None
I/O-IP
  • DDR4 SDRAM
  • Data width: 32
 None
Transceiver
  • E-Tile, HSSI_0_1, channels 0-11 active at 28 MBPS, NRZ
  • P-Tile, HSSI_0_0, PCIe Gen4×16, 500 MHz
  
HPS   None
HBM   None

At this point the power summary window shows a total power of 64 W for the FPGA when the maximum junction temperature (TJ-MAX) is set to 25°C. Changing the TJ-MAX to 90°C increases the total power to 73 W. The power increase is due to rise in static or leakage power. The static power is mainly a function of temperature.

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