AN 944: Thermal Modeling for Intel® Agilex™ FPGAs with the Intel® FPGA Power and Thermal Calculator

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ID 683810
Date 3/29/2021
Public
Document Table of Contents
Document Table of Contents x
1. List of Abbreviations 2. Introduction 3. Intel® Agilex™ FPGA Package Mechanical Design 4. Intel® Agilex™ FPGA Thermal Design Parameters 5. Thermal Design Process for Intel® Agilex™ Devices 6. Power and Thermal Calculator (PTC) for Intel® Agilex™ Devices 7. Example 2—Alternative Method of Analyzing Thermal Design 8. Document Revision History for AN 944: Thermal Modeling for Intel® Agilex™ FPGAs with the Intel® FPGA Power and Thermal Calculator
3. Intel® Agilex™ FPGA Package Mechanical Design x
3.1. Intel® Agilex™ Physical Package Structure
4. Intel® Agilex™ FPGA Thermal Design Parameters x
4.1. Intel® Agilex™ Compact Thermal Model (CTM) 4.2. Intel® Agilex™ Temperature Sensing 4.3. Thermal Sensor Accuracy
5. Thermal Design Process for Intel® Agilex™ Devices x
5.1. Thermal Parameter Dependencies and Accuracy
6. Power and Thermal Calculator (PTC) for Intel® Agilex™ Devices x
6.1. Device Selection and Analysis Example 6.2. Logic Design Information 6.3. Thermal Page and Thermal Design Parameters 6.4. CTM Model 6.5. Heat Sink 6.6. CFD Model
7. Example 2—Alternative Method of Analyzing Thermal Design x
7.1. Example 2—Full Length 1 Slot PCIe with 2 FPGAs 7.2. Thermal Design Optimization
1. List of Abbreviations
2. Introduction
3. Intel® Agilex™ FPGA Package Mechanical Design
4. Intel® Agilex™ FPGA Thermal Design Parameters
5. Thermal Design Process for Intel® Agilex™ Devices
6. Power and Thermal Calculator (PTC) for Intel® Agilex™ Devices
7. Example 2—Alternative Method of Analyzing Thermal Design
8. Document Revision History for AN 944: Thermal Modeling for Intel® Agilex™ FPGAs with the Intel® FPGA Power and Thermal Calculator

4. Intel® Agilex™ FPGA Thermal Design Parameters

The Intel® Agilex™ FPGA thermal parameters do not include the traditional junction-to-case thermal resistance (θJC) and junction-to-board thermal resistance (θJB) values, due to its multi-chip package construction. Instead of 2R resistor values, Intel provides a compact thermal model (CTM) of each package along with thermal parameters for each design through the Intel® FPGA Power and Thermal Calculator (PTC). The PTC thermal parameters include TJ, ΨCA, TAMBIENT, TCASE, ΨJC and total thermal power (TTP). The table below lists the thermal design parameters used in this document.
Table 2.  Thermal Design Parameters
Parameter Description
TA Ambient temperature, measured locally surrounding the FPGA. Measure the ambient temperature just upstream of a passive heat sink or at the fan inlet for an active heat sink. This value affects the junction temperature of the main FPGA core fabric die and its power dissipation.
TJ-MAX The maximum rated junction temperature of a die, or could be the design goal. For example, a particular die could have a manufacturer's specified TJ-MAX of 100°C, but designers can specify a TJ-MAX of less than 100°C as part of their design requirement.
Note: The active junction temperature of the package TJ varies across the package and die, and varies with design. The junction temperatures across the package are used by the PTC only for more accurate power and temperature calculation.
Power The PTC reports the power dissipation of each die individually.
Total Thermal Power (TTP) The total power dissipation of the device. This includes static power, with static power savings subtracted. The PTC reports this value in the Power Summary window.
ΨJC

The thermal resistance between each of the dies in the package and the center of the package integrated heat spreader. (See Figure 2).

A multi-chip module (MCM) such as the Intel® Agilex™ device will have as many ΨJC values as the number of dies in the package. The PTC reports the maximum ΨJC value which corresponds to the die with the highest temperature on the device. The ΨJC value is calculated by this equation:

ΨJC = (TJ-MAX - TCASE) / TTP

Note: ΨJC values are not constant for a specific package and change as the FPGA resource usage changes.
ΨCA The thermal resistance between the center of the package IHS and the ambient temperature. (See Figure 3.) ΨCA can be used as a figure of merit in assessing the required cooling solution for a design. For example, the lower the ΨCA value, the more aggressive cooling solution is needed. The value of ΨCA is calculated by this equation:

ΨCA = (TCASE - TA) / TTP

Note: ΨCA values are not constant for a specific package and change as the FPGA resource usage changes. You must recalculate this value for each design.
TCASE The temperature at the top center of the IHS. For a design to not exceed its TJ-MAX, the cooling solution must be able to maintain the TCASE temperature at or below the TCASE temperature reported by the PTC.
Note: TCASE values are not constant for a specific package and change as the FPGA resource usage changes.
Temperature Margin Temperature margin is calculated relative to a designated maximum junction temperature, TJ.
Power Margin Power margin indicates the power buffer available before the maximum junction temperature, TJ is exceeded.
Figure 2. Individual Die Thermal Resistance to the Top of IHS
Figure 3. Thermal ResistanceThe diagram shows the thermal resistance from each die to the IHS top surface and also to the air.
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