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1. Intel® Stratix® 10 Configuration User Guide 2. Intel® Stratix® 10 Configuration Details 3. Intel® Stratix® 10 Configuration Schemes 4. Including the Reset Release Intel® FPGA IP in Your Design 5. Remote System Update (RSU) 6. Intel® Stratix® 10 Configuration Features 7. Intel® Stratix® 10 Debugging Guide 8. Intel® Stratix® 10 Configuration User Guide Archives 9. Document Revision History for the Intel® Stratix® 10 Configuration User Guide
2.1. Intel® Stratix® 10 Configuration Timing Diagram 2.2. Configuration Flow Diagram 2.3. Device Response to Configuration and Reset Events 2.4. Additional Clock Requirements for HPS, PCIe* , eSRAM, and HBM2 2.5. Intel® Stratix® 10 Configuration Pins 2.6. Configuration Clocks 2.7. Maximum Configuration Time Estimation 2.8. Generating Compressed .sof File
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types 3.1.2. Enabling Avalon-ST Device Configuration 3.1.3. The AVST_READY Signal 3.1.4. RBF Configuration File Format 3.1.5. Avalon-ST Single-Device Configuration 3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme 3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
188.8.131.52.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins 184.108.40.206.2. PFL II IP Recommended Design Constraints for Using QSPI Flash 220.127.116.11.3. PFL II IP Recommended Design Constraints for using CFI Flash 18.104.22.168.4. PFL II IP Recommended Constraints for Other Input Pins 22.214.171.124.5. PFL II IP Recommended Constraints for Other Output Pins
3.2.1. AS Configuration Scheme Hardware Components and File Types 3.2.2. AS Single-Device Configuration 3.2.3. AS Using Multiple Serial Flash Devices 3.2.4. AS Configuration Timing Parameters 3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines 3.2.6. Programming Serial Flash Devices 3.2.7. Serial Flash Memory Layout 3.2.8. AS_CLK 3.2.9. Active Serial Configuration Software Settings 3.2.10. Intel® Quartus® Prime Programming Steps 3.2.11. Debugging Guidelines for the AS Configuration Scheme
5.1. Remote System Update Functional Description 5.2. Guidelines for Performing Remote System Update Functions for Non-HPS 5.3. Commands and Responses 5.4. Quad SPI Flash Layout 5.5. Generating Remote System Update Image Files Using the Programming File Generator 5.6. Remote System Update from FPGA Core Example
5.6.1. Prerequisites 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 5.6.3. Programming Flash Memory with the Initial Remote System Update Image 5.6.4. Reconfiguring the Device with an Application or Factory Image 5.6.5. Adding an Application Image 5.6.6. Removing an Application Image
7.1. Configuration Debugging Checklist 7.2. Intel® Stratix® 10 Configuration Architecture Overview 7.3. Understanding Configuration Status Using quartus_pgm command 7.4. SDM Debug Toolkit Overview 7.5. Configuration Pin Differences from Previous Device Families 7.6. Configuration File Format Differences 7.7. Understanding SEUs 7.8. Reading the Unique 64-Bit CHIP ID 7.9. E-Tile Transceivers May Fail To Configure 7.10. Understanding and Troubleshooting Configuration Pin Behavior
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
- 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
126.96.36.199.2. PFL II Signals
|pfl_nreset||Input||—||Asynchronous reset for the PFL II IP core. Pull high to enable FPGA configuration. To prevent FPGA configuration, pull low when you do not use the PFL II IP core. This pin does not affect the PFL II IP flash programming functionality.|
|pfl_flash_access_granted||Input||—||For system-level synchronization. A processor or any arbiter that controls access to the flash drives this input pin. To use the PFL II IP core function as the flash master pull this pin high. Driving the pfl_flash_access_granted pin low prevents the JTAG interface from accessing the flash and FPGA configuration.|
|pfl_clk||Input||—||User input clock for the device. This is the frequency you specify for the What is the external clock frequency? parameter on the Configuration tab of the PFL II IP. This frequency must not be higher than the maximum DCLK frequency you specify for FPGA during configuration. This pin is not available if you are only using the PFL II IP for flash programming.|
|fpga_pgm||Input||—||Determines the page for the configuration. This pin is not available if you are only using the PFL II IP for flash programming.|
|fpga_conf_done||Input||10 kΩ Pull-Up Resistor||Connects to the CONF_DONE pin of the FPGA. The FPGA releases the pin high if the configuration is successful. During FPGA configuration, this pin remains low. This pin is not available if you are only using the PFL II IP for flash programming.|
|fpga_nstatus||Input||10 kΩ Pull-Up Resistor||Connects to the nSTATUS pin of the FPGA. This pin is high before the FPGA configuration begins and must stay high during FPGA configuration. If a configuration error occurs, the FPGA pulls this pin low and the PFL II IP core stops reading the data from the flash memory device. This pin is not available if you are only using the PFL II IP for flash programming.|
When low initiates FPGA reconfiguration. To implement manual control of reconfiguration connect this pin to a switch. You can use this input to write your own logic in a CPLD to trigger reconfiguration via the PFL II IP. You can use pfl_nreconfigure to drive the fpga_nconfig output signal initiating reconfiguration. The pfl_clk pin registers this signal. This pin is not available if you are only using the PFL II IP for flash programming.
|pfl_flash_access_request||Output||—||For system-level synchronization. When necessary, this pin connects to a processor or an arbiter. The PFL II IP core drives this pin high when the JTAG interface accesses the flash or the PFL II IP configures the FPGA. This output pin works in conjunction with the flash_noe and flash_nwe pins.|
|flash_addr||Output||—||The flash memory address. The width of the address bus depends on the density of the flash memory device and the width of the flash_data bus. Intel recommends that you turn On the Set flash bus pins to tri-state when not in use option in the PFL II .|
|flash_data||Input or Output (bidirectional pin)||—||Bidirectional data bus to transmit or receive 8-, 16-, or 32-bit data. Intel recommends that you turn On the Set flash bus pins to tri-state when not in use option in the PFL II. 13|
|flash_nce||Output||—||Connects to the nCE pin of the flash memory device. A low signal enables the flash memory device. Use this bus for multiple flash memory device support. The flash_nce pin connects to each nCE pin of all the connected flash memory devices. The width of this port depends on the number of flash memory devices in the chain.|
|flash_nwe||Output||—||Connects to the nWE pin of the flash memory device. When low enables write operations to the flash memory device.|
|flash_noe||Output||—||Connects to the nOE pin of the flash memory device. When low enables the outputs of the flash memory device during a read operation.|
|flash_clk||Output||—||For burst mode. Connects to the CLK input pin of the flash memory device. The active edges of CLK increment the flash memory device internal address counter. The flash_clk frequency is half of the pfl_clk frequency in burst mode for a single CFI flash. In dual CFI flash solution, the flash_clk frequency runs at a quarter of the pfl_clk frequency. Use this pin for burst mode only. Do not connect these pins from the flash memory device to the host if you are not using burst mode.|
|flash_nadv||Output||—||For burst mode. Connects to the address valid input pin of the flash memory device. Use this signal to latch the start address. Use this pin for burst mode only. Do not connect these pins from the flash memory device to the host if you are not using burst mode.|
|flash_nreset||Output||—||Connects to the reset pin of the flash memory device. A low signal resets the flash memory device.|
|fpga_nconfig||Open Drain Output||10-kW Pull-Up Resistor||Connects to the nCONFIG pin of the FPGA. A low pulse resets the FPGA and initiates configuration. These pins are not available for the flash programming option in the PFL II IP core. 13|
|pfl_reset_watchdog||Input||—||A switch signal to reset the watchdog timer before the watchdog timer times out. To reset the watchdog timer hold the signal high or low for at least two pfl_clk clock cycles.|
|pfl_watchdog_error||Output||—||When high indicates an error condition to the watchdog timer.|
13 Intel recommends that you do not insert logic between the PFL II pins and the host I/O pins, especially on the flash_data and fpga_nconfig pins.
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