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- 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image
2.4. Additional Clock Requirements for HPS, PCIe* , eSRAM, and HBM2
- HBM2: pll_ref_clk and ext_core_clk
- eSRAM: CLK_ESRAM_[0,1]p and CLK_ESRAM_[0,1]n
- HPS: HPS_OSC_CLK, when HPS enabled 3
- HPS EMIF: pll_ref_clk
- L- and H-tile PCIe* channels: REFCLK_GXB
- E-tile: REFCLK_GXE
In the Intel® Stratix® 10 TX/MX devices, when using PRESERVE_UNUSED_XCVR_CHANNEL_QSF assignment to protect unused channels by enabling transceiver circuits, you must provide a free-running and stable reference clock to the transceiver circuit.
Intel® Quartus® Prime Pro Edition software allows you to configure the HPS prior to FPGA configuration. To enable this option, select HPS First in the Assignments > Device > Device and Pin Options > Configuration > HPS/FPGA Configuration order dialog box.
HPS First Configuration
- HPS reference clock: HPS_OSC_CLK
- HPS EMIF (when in use): pll_ref_clk
- E-tile transceivers: REFCLK_GXE
The remaining clocks specified in the FPGA Configuration must be fully operational prior the FPGA core logic configuration, also called phase 2 configuration. For more information on HPS boot first mode, refer to the Intel® Stratix® 10 SoC FPGA Boot User Guide.
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