Intel® Stratix® 10 Configuration User Guide

ID 683762
Date 1/10/2022

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3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines

You must minimize the skew on the AS data pins.

Skew delay includes the following elements:

  • The delay due to the differences in board traces lengths on the PCB
  • The capacitance loading of the flash device

The table below lists the maximum allowable skew delay depending on the AS_CLK frequency. Intel recommends that you to perform IBIS simulations to ensure that the skew delay does not exceed the maximum delay specified in this table.

Table 33.  Maximum Skew for AS Data Pins in Nanoseconds (ns)
Symbol Description Frequency Min Typical Max
Text_skew Skew delay for AS_DATA for the AS_CLK frequency specified 125 MHz 4.00
115 MHz 4.20
100 MHz 5.0
<100 MHz 5.0

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