Intel® Stratix® 10 Configuration User Guide

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ID 683762
Date 1/10/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 Configuration User Guide 2. Intel® Stratix® 10 Configuration Details 3. Intel® Stratix® 10 Configuration Schemes 4. Including the Reset Release Intel® FPGA IP in Your Design 5. Remote System Update (RSU) 6. Intel® Stratix® 10 Configuration Features 7. Intel® Stratix® 10 Debugging Guide 8. Intel® Stratix® 10 Configuration User Guide Archives 9. Document Revision History for the Intel® Stratix® 10 Configuration User Guide
1. Intel® Stratix® 10 Configuration User Guide x
1.1. Intel® Stratix® 10 Configuration Overview 1.2. Intel® Stratix® 10 Configuration Architecture
1.1. Intel® Stratix® 10 Configuration Overview x
1.1.1. Configuration and Related Signals 1.1.2. Intel Download Cables Supporting Configuration in Intel® Stratix® 10 Devices
1.2. Intel® Stratix® 10 Configuration Architecture x
1.2.1. Secure Device Manager
1.2.1. Secure Device Manager x
1.2.1.1. Restricting Security Features 1.2.1.2. Updating the SDM Firmware 1.2.1.3. Specifying Boot Order for Intel® Stratix® 10 SoC Devices
2. Intel® Stratix® 10 Configuration Details x
2.1. Intel® Stratix® 10 Configuration Timing Diagram 2.2. Configuration Flow Diagram 2.3. Device Response to Configuration and Reset Events 2.4. Additional Clock Requirements for HPS, PCIe* , eSRAM, and HBM2 2.5. Intel® Stratix® 10 Configuration Pins 2.6. Configuration Clocks 2.7. Maximum Configuration Time Estimation 2.8. Generating Compressed .sof File
2.5. Intel® Stratix® 10 Configuration Pins x
2.5.1. SDM Pin Mapping 2.5.2. MSEL Settings 2.5.3. Device Configuration Pins for Optional Configuration Signals
2.5.3. Device Configuration Pins for Optional Configuration Signals x
2.5.3.1. Specifying Optional Configuration Pins 2.5.3.2. Enabling Dual-Purpose Pins 2.5.3.3. Configuration Pins I/O Standard, Drive Strength, and IBIS Model 2.5.3.4. SDM I/O Pins for Power Management and SmartVID 2.5.3.5. Specifying Pins for Partial Reconfiguration (PR)
2.5.3.1. Specifying Optional Configuration Pins x
2.5.3.1.1. nCONFIG 2.5.3.1.2. nSTATUS 2.5.3.1.3. CONF_DONE and INIT_DONE 2.5.3.1.4. SDM_IO Pins
2.6. Configuration Clocks x
2.6.1. Setting Configuration Clock Source 2.6.2. OSC_CLK_1 Clock Input
3. Intel® Stratix® 10 Configuration Schemes x
3.1. Avalon-ST Configuration 3.2. AS Configuration 3.3. JTAG Configuration
3.1. Avalon-ST Configuration x
3.1.1. Avalon® -ST Configuration Scheme Hardware Components and File Types 3.1.2. Enabling Avalon-ST Device Configuration 3.1.3. The AVST_READY Signal 3.1.4. RBF Configuration File Format 3.1.5. Avalon-ST Single-Device Configuration 3.1.6. Debugging Guidelines for the Avalon® -ST Configuration Scheme 3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core
3.1.7. IP for Use with the Avalon® -ST Configuration Scheme: Intel FPGA Parallel Flash Loader II IP Core x
3.1.7.1. Functional Description 3.1.7.2. Designing with the PFL II IP Core for Avalon-ST Single Device Configuration 3.1.7.3. Generating the PFL II IP Core 3.1.7.4. Constraining the PFL II IP Core 3.1.7.5. Using the PFL II IP Core
3.1.7.1. Functional Description x
3.1.7.1.1. Generating and Programming a .pof into CFI Flash 3.1.7.1.2. Implementing Multiple Pages in the Flash .pof 3.1.7.1.3. Storing Option Bits 3.1.7.1.4. Verifying the Option Bit Start and End Addresses 3.1.7.1.5. Implementing Page Mode and Option Bits in the CFI Flash Memory Device
3.1.7.2. Designing with the PFL II IP Core for Avalon-ST Single Device Configuration x
3.1.7.2.1. PFL II Parameters 3.1.7.2.2. PFL II Signals
3.1.7.3. Generating the PFL II IP Core x
3.1.7.3.1. Controlling Avalon-ST Configuration with PFL II IP Core 3.1.7.3.2. Mapping PFL II IP Core and Flash Address 3.1.7.3.3. Creating a Single PFL II IP for Programming and Configuration 3.1.7.3.4. Creating Separate PFL II Functions
3.1.7.4. Constraining the PFL II IP Core x
3.1.7.4.1. PFL II IP Recommended Design Constraints to FPGA Avalon-ST Pins 3.1.7.4.2. PFL II IP Recommended Design Constraints for Using QSPI Flash 3.1.7.4.3. PFL II IP Recommended Design Constraints for using CFI Flash 3.1.7.4.4. PFL II IP Recommended Constraints for Other Input Pins 3.1.7.4.5. PFL II IP Recommended Constraints for Other Output Pins
3.1.7.5. Using the PFL II IP Core x
3.1.7.5.1. Converting .sof to .pof File 3.1.7.5.2. Programming CPLDs and Flash Memory Devices Sequentially 3.1.7.5.3. Programming CPLDs and Flash Memory Devices Separately 3.1.7.5.4. Defining New CFI Flash Memory Device
3.2. AS Configuration x
3.2.1. AS Configuration Scheme Hardware Components and File Types 3.2.2. AS Single-Device Configuration 3.2.3. AS Using Multiple Serial Flash Devices 3.2.4. AS Configuration Timing Parameters 3.2.5. Maximum Allowable External AS_DATA Pin Skew Delay Guidelines 3.2.6. Programming Serial Flash Devices 3.2.7. Serial Flash Memory Layout 3.2.8. AS_CLK 3.2.9. Active Serial Configuration Software Settings 3.2.10. Intel® Quartus® Prime Programming Steps 3.2.11. Debugging Guidelines for the AS Configuration Scheme
3.2.6. Programming Serial Flash Devices x
3.2.6.1. Programming Serial Flash Devices using the AS Interface 3.2.6.2. Programming Serial Flash Devices using the JTAG Interface
3.2.7. Serial Flash Memory Layout x
3.2.7.1. Understanding Quad SPI Flash Byte-Addressing
3.2.10. Intel® Quartus® Prime Programming Steps x
3.2.10.1. Generating Programming Files using the Programming File Generator 3.2.10.2. Programming .pof files into Serial Flash Device 3.2.10.3. Programming .jic files into Serial Flash Device
3.3. JTAG Configuration x
3.3.1. JTAG Configuration Scheme Hardware Components and File Types 3.3.2. JTAG Device Configuration 3.3.3. JTAG Multi-Device Configuration 3.3.4. Debugging Guidelines for the JTAG Configuration Scheme
3.3.2. JTAG Device Configuration x
3.3.2.1. JTAG Single-Device Configuration using Download Cable Connections 3.3.2.2. JTAG Single-Device Configuration using a Microprocessor
3.3.3. JTAG Multi-Device Configuration x
3.3.3.1. JTAG Multi-Device Configuration using Download Cable
4. Including the Reset Release Intel® FPGA IP in Your Design x
4.1. Understanding the Reset Release IP Requirement 4.2. Instantiating the Reset Release IP In Your Design 4.3. Gating the PLL Reset Signal 4.4. Guidance When Using Partial Reconfiguration (PR) 4.5. Detailed Description of Device Configuration
4.5. Detailed Description of Device Configuration x
4.5.1. Device Initialization 4.5.2. Preventing Register Initialization During Power-On 4.5.3. Embedded Memory Block Initial Conditions 4.5.4. Protecting State Machine Logic
5. Remote System Update (RSU) x
5.1. Remote System Update Functional Description 5.2. Guidelines for Performing Remote System Update Functions for Non-HPS 5.3. Commands and Responses 5.4. Quad SPI Flash Layout 5.5. Generating Remote System Update Image Files Using the Programming File Generator 5.6. Remote System Update from FPGA Core Example
5.1. Remote System Update Functional Description x
5.1.1. RSU Glossary 5.1.2. Remote System Update Using AS Configuration 5.1.3. Remote System Update Configuration Images 5.1.4. Remote System Update Configuration Sequence 5.1.5. RSU Recovery from Corrupted Images 5.1.6. Updates with the Factory Update Image
5.3. Commands and Responses x
5.3.1. Operation Commands 5.3.2. Error Code Responses 5.3.3. Error Code Recovery
5.4. Quad SPI Flash Layout x
5.4.1. High Level Flash Layout 5.4.2. Detailed Quad SPI Flash Layout
5.4.1. High Level Flash Layout x
5.4.1.1. Standard (non-RSU) Image Layout in Flash 5.4.1.2. RSU Image Layout in Flash – SDM Perspective 5.4.1.3. RSU Image Layout – Your Perspective
5.4.1.2. RSU Image Layout in Flash – SDM Perspective x
5.4.1.2.1. Firmware Version Information
5.4.2. Detailed Quad SPI Flash Layout x
5.4.2.1. RSU Image Sub-Partitions Layout 5.4.2.2. Sub-Partition Table Layout 5.4.2.3. Configuration Pointer Block Layout 5.4.2.4. Modifying the List of Application Images 5.4.2.5. Application Image Layout
5.5. Generating Remote System Update Image Files Using the Programming File Generator x
5.5.1. Generating the Initial RSU Image 5.5.2. Generating an Application Image 5.5.3. Generating a Factory Update Image 5.5.4. Command Sequence To Perform Quad SPI Operations
5.5.1. Generating the Initial RSU Image x
5.5.1.1. Generating the Initial RSU Image Using SOF Files 5.5.1.2. Generating the Initial RSU Image Using RBF Files 5.5.1.3. Updating Decision Firmware
5.6. Remote System Update from FPGA Core Example x
5.6.1. Prerequisites 5.6.2. Creating Initial Flash Image Containing Bitstreams for Factory Image and One Application Image 5.6.3. Programming Flash Memory with the Initial Remote System Update Image 5.6.4. Reconfiguring the Device with an Application or Factory Image 5.6.5. Adding an Application Image 5.6.6. Removing an Application Image
6. Intel® Stratix® 10 Configuration Features x
6.1. Device Security 6.2. Configuration via Protocol 6.3. Partial Reconfiguration
7. Intel® Stratix® 10 Debugging Guide x
7.1. Configuration Debugging Checklist 7.2. Intel® Stratix® 10 Configuration Architecture Overview 7.3. Understanding Configuration Status Using quartus_pgm command 7.4. SDM Debug Toolkit Overview 7.5. Configuration Pin Differences from Previous Device Families 7.6. Configuration File Format Differences 7.7. Understanding SEUs 7.8. Reading the Unique 64-Bit CHIP ID 7.9. E-Tile Transceivers May Fail To Configure 7.10. Understanding and Troubleshooting Configuration Pin Behavior
7.4. SDM Debug Toolkit Overview x
7.4.1. Using the SDM Debug Toolkit
1. Intel® Stratix® 10 Configuration User Guide
2. Intel® Stratix® 10 Configuration Details
3. Intel® Stratix® 10 Configuration Schemes
4. Including the Reset Release Intel® FPGA IP in Your Design
5. Remote System Update (RSU)
6. Intel® Stratix® 10 Configuration Features
7. Intel® Stratix® 10 Debugging Guide
8. Intel® Stratix® 10 Configuration User Guide Archives
9. Document Revision History for the Intel® Stratix® 10 Configuration User Guide

4.1. Understanding the Reset Release IP Requirement

Intel® Stratix® 10 devices use a parallel, sector-based architecture that distributes the core fabric logic across multiple sectors. Device configuration proceeds in parallel with each Local Sector Manager (LSM) configuring its own sector. Consequently, FPGA registers and core logic do not exit reset at exactly the same time, as has always been the case in previous families.

The continual increases in clock frequency, device size, and design complexity now necessitate a reset strategy that considers the possible effects of slight differences in the release from reset. The Reset Release Intel FPGA IP holds a control circuit in reset until the device has fully entered user mode. The Reset Release FPGA IP generates an inverted version of the internal INIT_DONE signal, nINIT_DONE for use in your design.

After nINIT_DONE asserts (low), all logic is in user mode and operates normally. You can use the nINIT_DONE signal in one of the following ways:

  • To gate an external or internal reset.
  • To gate the reset input to the transceiver and I/O PLLs.
  • To gate the write enable of design blocks such as embedded memory blocks, state machine, and shift registers.
  • To synchronously drive register reset input ports in your design.
Attention: When you instantiate Reset Release Intel FPGA IP in your design, the Intel® Quartus® Prime Fitter selects one Local Sector Manager (LSM) to output the nINIT_DONE signal. Multiple instances results in some skew between the nINIT_DONE signals.
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