JESD204B Intel® FPGA IP Release Notes

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ID 683737
Date 7/19/2024
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1. JESD204B Intel FPGA IP Release Notes
1. JESD204B Intel FPGA IP Release Notes x
1.1. JESD204B Intel FPGA IP v20.2.1 1.2. JESD204B Intel FPGA IP v19.2.0 1.3. JESD204B Intel FPGA IP v19.2.0 1.4. JESD204B Intel FPGA IP v19.1 1.5. JESD204B Intel FPGA IP v18.1 1.6. JESD204B Intel FPGA IP v18.0 1.7. JESD204B IP Core v17.1 1.8. JESD204B IP Core v17.0 1.9. JESD204B IP Core v16.1 1.10. JESD204B IP Core v16.0 1.11. JESD204B IP Core v15.1 1.12. JESD204B IP Core v15.0 1.13. JESD204B IP Core v14.1 1.14. JESD204B Intel® FPGA IP User Guide Archives 1.15. JESD204B Stratix® 10 FPGA IP Design Example User Guide Archives
1. JESD204B Intel FPGA IP Release Notes

1.7. JESD204B IP Core v17.1

Table 7.  v17.1 November 2017
Description Impact
Added support for Stratix® 10 FPGA devices. Stratix® 10 devices are now supported in the 17.1 Quartus® Prime Pro Edition.
Added a new parameter—Provide Separate Reconfiguration Interface for Each Channel. Available in Quartus® Prime Pro Edition only.

Supports up to 12.5Gbps characterized to JESD204B specification.

Supports up to 16Gbps not characterized to the JESD204B specification.

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In previous versions of the JESD204B IP core design example for Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in Quartus® Prime version 17.1.

This issue affects designs that use Arria® 10 devices. If you are upgrading designs that have these additional constraints from the previous versions of Quartus® Prime to version 17.1, you must revise the constraints. Refer to the KDB page for more information.
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