1.6. JESD204B IP Core v17.1
|Added support for Intel® Stratix® 10 FPGA devices.||Intel® Stratix® 10 devices are now supported in the 17.1 Intel® Quartus® Prime Pro Edition.|
|Added a new parameter—Provide Separate Reconfiguration Interface for Each Channel.||Available in Intel® Quartus® Prime Pro Edition only.|
Supports up to 12.5Gbps characterized to JESD204B specification.
Supports up to 16Gbps not characterized to the JESD204B specification.
In previous versions of the JESD204B IP core design example for Intel® Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in Intel® Quartus® Prime version 17.1.
|This issue affects designs that use Intel® Arria® 10 devices. If you are upgrading designs that have these additional constraints from the previous versions of Intel® Quartus® Prime to version 17.1, you must revise the constraints. Refer to the KDB page for more information.|
Did you find the information on this page useful?