JESD204B Intel FPGA IP Release Notes

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ID 683737
Date 12/16/2019
Public
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1. JESD204B Intel FPGA IP Release Notes
1. JESD204B Intel FPGA IP Release Notes x
1.1. JESD204B Intel FPGA IP v19.2.0 1.2. JESD204B Intel FPGA IP v19.2.0 1.3. JESD204B Intel FPGA IP v19.1 1.4. JESD204B Intel FPGA IP v18.1 1.5. JESD204B Intel FPGA IP v18.0 1.6. JESD204B IP Core v17.1 1.7. JESD204B IP Core v17.0 1.8. JESD204B IP Core v16.1 1.9. JESD204B IP Core v16.0 1.10. JESD204B IP Core v15.1 1.11. JESD204B IP Core v15.0 1.12. JESD204B IP Core v14.1 1.13. JESD204B Intel® FPGA IP User Guide Archives 1.14. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
1. JESD204B Intel FPGA IP Release Notes

1.1. JESD204B Intel FPGA IP v19.2.0

Table 1.  v19.2.0 2019.12.16
Intel® Quartus® Prime Version Description Impact
19.4 Updated the supported maximum data rate to 19.2 Gbps for Intel Agilex® 7 devices. –
Enabled hardware design example for Intel Agilex® 7 devices.

You can generate the design example using the Intel Agilex® 7 Signal Integrity development kit.

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