Visible to Intel only — GUID: sfg1493951247899
Ixiasoft
1.1. JESD204B Intel FPGA IP v20.2.1
1.2. JESD204B Intel FPGA IP v19.2.0
1.3. JESD204B Intel FPGA IP v19.2.0
1.4. JESD204B Intel FPGA IP v19.1
1.5. JESD204B Intel FPGA IP v18.1
1.6. JESD204B Intel FPGA IP v18.0
1.7. JESD204B IP Core v17.1
1.8. JESD204B IP Core v17.0
1.9. JESD204B IP Core v16.1
1.10. JESD204B IP Core v16.0
1.11. JESD204B IP Core v15.1
1.12. JESD204B IP Core v15.0
1.13. JESD204B IP Core v14.1
1.14. JESD204B Intel® FPGA IP User Guide Archives
1.15. JESD204B Stratix® 10 FPGA IP Design Example User Guide Archives
Visible to Intel only — GUID: sfg1493951247899
Ixiasoft
1.8. JESD204B IP Core v17.0
| Description | Impact |
|---|---|
| Added support for Stratix® 10 FPGA devices. | Stratix® 10 devices are not supported in the Quartus® Prime Pro Edition. For more information, contact Intel. |
| Added somf[] for transmitter signal. | — |
| Updated data path preset value to simplex TX and simplex RX. | — |
|
This feature is available only for Arria® 10 and Stratix® 10 device family. |