JESD204B Intel FPGA IP Release Notes

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ID 683737
Date 12/16/2019
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1. JESD204B Intel FPGA IP Release Notes
1. JESD204B Intel FPGA IP Release Notes x
1.1. JESD204B Intel FPGA IP v19.2.0 1.2. JESD204B Intel FPGA IP v19.2.0 1.3. JESD204B Intel FPGA IP v19.1 1.4. JESD204B Intel FPGA IP v18.1 1.5. JESD204B Intel FPGA IP v18.0 1.6. JESD204B IP Core v17.1 1.7. JESD204B IP Core v17.0 1.8. JESD204B IP Core v16.1 1.9. JESD204B IP Core v16.0 1.10. JESD204B IP Core v15.1 1.11. JESD204B IP Core v15.0 1.12. JESD204B IP Core v14.1 1.13. JESD204B Intel® FPGA IP User Guide Archives 1.14. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
1. JESD204B Intel FPGA IP Release Notes

1.3. JESD204B Intel FPGA IP v19.1

Table 3.  v19.1 April 2019
Description Impact
Added support for Intel® Stratix® 10 E-tile devices. Merging of simplex TX and RX channels is not supported. These changes are optional. If you do not manually upgrade your IP core and select E-tile for Transceiver Tile, it does not have these new features.

Added the Transceiver Tile parameter. This parameter is available when you target an Intel® Stratix® 10 device that supports both H-tile and E-tile. You can choose the tile that you want to use for your design.

Added the following signals that are applicable only for Intel® Stratix® 10 E-tile devices.
  • phy_tx_ready
  • phy_rx_ready
  • phy_tx_pma_ready
  • phy_rx_pma_ready
  • phy_tx_rst_n
  • phy_rx_rst_n
  • tx_serial_data_n
  • rx_serial_data_n
Renamed the Enable Altera Debug Master Endpoint parameter to Enable Native PHY Debug Master Endpoint as per Intel rebranding in the Intel Quartus Prime Pro Edition software. The Intel Quartus Prime Standard Edition software still uses Enable Altera Debug Master Endpoint. —
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