AN 908: Enabling 4G Wireless Acceleration in FlexRAN: for the Intel® FPGA Programmable Acceleration Card N3000

ID 683736
Date 1/30/2020

2.3.1. O-RAN Compression and Decompression

The compression and decompression IP supports both block floating point and Mu-Law compression methods.
Figure 13. Compression and Decompression IO

Internally, the design collects the 12 resource elements in a resource block and determines the maximum magnitude. It then performs block floating-point shifting and Mu-Law compression or decompression.

Figure 14. Compression and Decompression 16:8 bit Example