2.2.1. 4G Channel Coder Throughput
The Intel FPGA PAC N3000 4G channel coder contains four encoders and six decoders. The throughput depends on the traffic model.
Baseline values include:
- Max code block size 6,144 downlink, 5,824 uplink
- Max transport block size 75,376 down and uplink
- 1 ms TTI
- Fmax = 275 MHz
Uplink throughput (decoding path) is 10 x (75376 + 13*24 +24) bits in 500 µs, which is 1.5142 Gbits/s @ 8 iterations. The decoders can decode 10 x 13 = 130 code-blocks of length 5,824 bits in 500 µs @ 8 iterations
Downlink throughput (encoding path) is 10 x 2 x (75376 + 13 *24 +24) bits in 333 µs, which is 4.5473 Gbits/s. The encoders can encode 10 x 2 x 13 = 260 code-blocks of length 6,144 bits in 333 µs.
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