AN 908: Enabling 4G Wireless Acceleration in FlexRAN: for the Intel® FPGA Programmable Acceleration Card N3000

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ID 683736
Date 1/30/2020
Public
Document Table of Contents
Document Table of Contents x
1. About the 4G Wireless Acceleration Reference Design 2. 4G User Image Description 3. Document Revision History for AN 908: Enabling 4G Wireless Acceleration in FlexRAN for the Intel® FPGA Programmable Acceleration Card N3000
1. About the 4G Wireless Acceleration Reference Design x
1.1. 4G User Image Features 1.2. About the Intel PAC N3000
1.2. About the Intel PAC N3000 x
1.2.1. Factory Image for 2x2x25 GbE
2. 4G User Image Description x
2.1. User Image Power Management 2.2. 4G Channel Coder 2.3. Fronthaul IO 2.4. User Image Software
2.2. 4G Channel Coder x
2.2.1. 4G Channel Coder Throughput 2.2.2. 4G Turbo-V Encoder and Decoder Tests 2.2.3. 4G VRAN Universal Verification Methodology
2.3. Fronthaul IO x
2.3.1. O-RAN Compression and Decompression
1. About the 4G Wireless Acceleration Reference Design
2. 4G User Image Description
3. Document Revision History for AN 908: Enabling 4G Wireless Acceleration in FlexRAN for the Intel® FPGA Programmable Acceleration Card N3000

2.2. 4G Channel Coder

You should send and receive code blocks for the encoder and decoder over PCIe to or from the host using the descriptor format defined in the Data Plane Development Kit (DPDK) and the baseband device (bbdev).

The channel coders queue and process these blocks based on the load balancing decisions.

Figure 4. 4G Channel Coder
Figure 5. 4G Channel Downlink FEC AcceleratorThe downlink FEC accelerator ((Intel Turbo-V FPGA IP)) consists of a code block CRC attachment block and a Turbo encoder (Intel Turbo FPGA IP) and rate matcher. The input data is 8-bit wide and the output data is 24-bit wide. The rate matcher consists of three interleavers and bit selector and bit collector.
Figure 6. 4G Channel Uplink FEC AcceleratorThe uplink FEC accelerator (Intel Turbo-V FPGA IP) consists of an interleaver and a turbo decoder (Intel Turbo FPGA IP).
Figure 7. Deinterleaver
Figure 8. Bit Collector

Section Content
4G Channel Coder Throughput
4G Turbo-V Encoder and Decoder Tests
4G VRAN Universal Verification Methodology

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