AN 908: Enabling 4G Wireless Acceleration in FlexRAN: for the Intel® FPGA Programmable Acceleration Card N3000

ID 683736
Date 1/30/2020

2.2. 4G Channel Coder

You should send and receive code blocks for the encoder and decoder over PCIe to or from the host using the descriptor format defined in the Data Plane Development Kit (DPDK) and the baseband device (bbdev).

The channel coders queue and process these blocks based on the load balancing decisions.

Figure 4. 4G Channel Coder
Figure 5. 4G Channel Downlink FEC AcceleratorThe downlink FEC accelerator ((Intel Turbo-V FPGA IP)) consists of a code block CRC attachment block and a Turbo encoder (Intel Turbo FPGA IP) and rate matcher. The input data is 8-bit wide and the output data is 24-bit wide. The rate matcher consists of three interleavers and bit selector and bit collector.
Figure 6. 4G Channel Uplink FEC AcceleratorThe uplink FEC accelerator (Intel Turbo-V FPGA IP) consists of an interleaver and a turbo decoder (Intel Turbo FPGA IP).
Figure 7. Deinterleaver
Figure 8. Bit Collector