Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 1/04/2023
Public
Document Table of Contents

coreclkout_hip can drive the Application Layer clock along with the pld_clk input to the IP core. The pld_clk can optionally be sourced by a different clock than coreclkout_hip. The pld_clk minimum frequency cannot be lower than the coreclkout_hip frequency. Based on specific Application Layer constraints, a PLL can be used to derive the desired frequency.