Intel® Stratix® 10 TX Device Overview

ID 683717
Date 8/18/2022
Public
Document Table of Contents

1.1. Intel® Stratix® 10 TX Devices

In addition to delivering over 8 Tbps of transceiver bandwidth in a single package, Intel® Stratix® 10 TX devices offer up to 1 GHz core fabric performance and contain up to 2.8 million LEs in a monolithic fabric. They also feature up to 144 general purpose transceivers on separate transceiver tiles, and 2666 Mbps DDR4 external memory interface performance. The dual mode transceivers are capable of data rates up to 57.8 Gbps PAM4 / 28.9 Gbps NRZ for both short reach and backplane driving applications. Select devices contain an embedded hard processor system (HPS) based on an application-class quad-core 64 bit Arm* Cortex* -A53, running at clock rates up to 1.5 GHz.

These devices are optimized for FPGA applications that require the highest transceiver bandwidth, and the highest core fabric performance, with the power efficiency of Intel’s 14 nm tri-gate process technology.

The high-performance monolithic FPGA fabric is based on the new Intel® Hyperflex™ core architecture that includes additional Hyper-Registers everywhere throughout the interconnect routing and at the inputs of all functional blocks. The core fabric also contains an enhanced logic array utilizing Intel’s adaptive logic module (ALM) and a rich set of high performance building blocks including:

  • eSRAM (47.25 Mbit) embedded memory blocks (available in select devices)
  • M20K (20 Kb) embedded memory blocks
  • Variable precision DSP blocks with IEEE 754 compliant hard floating-point
  • Fractional synthesis and integer PLLs
  • Hard memory controllers and PHY for external memory interfaces
  • General purpose IO cells

To clock these building blocks, Intel® Stratix® 10 TX devices use programmable clock tree synthesis, which uses dedicated clock tree routing to synthesize only those branches of the clock trees required for the application. All devices support in-system, fine-grained partial reconfiguration of the logic array, allowing logic to be added and subtracted from the system while it is operating. The high speed serial transceivers contain both the physical medium attachment (PMA) and the physical coding sublayer (PCS), which can be used to implement a variety of industry standard and proprietary protocols. In addition to the hard PCS, Intel® Stratix® 10 TX devices contain hard PCI Express® IP that supports Gen1/Gen2/Gen3 rates in x1/x2/x4/x8/x16 lane configurations, and 10/25/100 Gbps Ethernet MAC with dedicated Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514). The hard PCS, PCI Express IP and 10/25/100 Gbps Ethernet MAC and FEC IP free up valuable core logic resources, save power, and increase your productivity.

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