Stratix® 10 TX Device Overview

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ID 683717
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 TX Device Overview
1. Intel® Stratix® 10 TX Device Overview x
1.1. Intel® Stratix® 10 TX Devices 1.2. Innovations in Intel® Stratix® 10 TX Devices 1.3. Intel® Stratix® 10 TX Features Summary 1.4. Intel® Stratix® 10 TX Block Diagram 1.5. Intel® Stratix® 10 TX Family Plan 1.6. Intel® Hyperflex™ Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Intel® Stratix® 10 TX Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Ethernet MAC, Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) 1.11. 10G Ethernet Hard IP 1.12. Interlaken PCS Hard IP 1.13. External Memory and General Purpose I/O 1.14. Adaptive Logic Module (ALM) 1.15. Core Clocking 1.16. Fractional Synthesis PLLs and I/O PLLs 1.17. Internal Embedded Memory 1.18. Variable Precision DSP Block 1.19. Hard Processor System (HPS) 1.20. Power Management 1.21. Device Configuration and Secure Device Manager (SDM) 1.22. Device Security 1.23. Configuration via Protocol Using PCI Express* 1.24. Partial and Dynamic Reconfiguration 1.25. Fast Forward Compile 1.26. Single Event Upset (SEU) Error Detection and Correction 1.27. Document Revision History for the Intel® Stratix® 10 TX Device Overview
1.1. Intel® Stratix® 10 TX Devices x
1.1.1. Available Options
1.8. Intel® Stratix® 10 TX Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.19. Hard Processor System (HPS) x
1.19.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 TX Device Overview

1.5. Intel® Stratix® 10 TX Family Plan

Table 4.   Intel® Stratix® 10 TX Family Plan—FPGA Core (part 1)

Intel® Stratix® 10 TX Device Name

Logic Elements (KLE)

eSRAM Blocks eSRAM Mbits

M20K Blocks

M20K Mbits

MLAB Counts

MLAB Mbits

18x19 Multi- pliers 1

HPS
TX 400 378 - - 1,537 30 3,276 2 1,296 Yes
TX 850 841 - - 3,477 68 7,124 4 4,032 Yes
TX 1100 1,325 - - 5,461 107 11,556 7 5,184 Yes
TX 1650 1679 2 94.5 6,162 120 14,230 9 6,652 -
TX 2100 2,073 2 94.5 6,847 134 17,856 11 7,920 -
TX 2500 2,422 - - 9,963 195 20,529 13 10,022 Yes
TX 2800 2,753 - - 11,721 229 23,796 15 11,520 Yes
Table 5.   Intel® Stratix® 10 TX Family Plan - Interconnects, PLLs and Hard IP (part 2)
Stratix 10 TX Device Name Package Interconnects PLLs Hard IP
GPIOs Transceiver fPLLs I/O PLLs PCIe Hard IP Blocks 50/100 GbE MACs 10/25/100 GbE MACs
TX 400 HF35 (F1152) 384 24 0 8 0 0 4
TX 850 NF43 (F1760) 440 48 8 16 1 1 4
TX 850 SF50 (F2397) 440 72 8 16 1 1 8
TX 1100 NF43 (F1760) 440 48 8 16 1 1 4
TX 1100 SF50 (F2397) 440 72 8 16 1 1 8
TX 1650 UF50 (F2397) 440 96 8 16 1 1 12
TX 2100 UF50 (F2397) 440 96 8 16 1 1 12
TX 2500 UF50 (F2397) 440 96 8 24 1 1 12
TX 2500 YF55 (F2912) 296 144 8 24 1 1 20
TX 2800 UF50 (F2397) 440 96 8 24 1 1 12
TX 2800 YF55 (F2912) 296 144 8 24 1 1 20
Table 6.   Intel® Stratix® 10 TX Package Plan Cell legend: General Purpose I/Os, High-Voltage I/Os, LVDS Pairs, E-tile Transceivers, H-tile Transceivers. 2 3 4 5 6
Intel® Stratix® 10 TX Device Name

F1152

HF35 - 24 Transceivers

(35 x 35 mm2)

F1760

NF43 - 48 Transceivers

(42.5 x 42.5 mm2)

F2397

SF50 - 72 Transceivers

UF50 - 96 Transceivers

(50 x 50 mm2)

F2912

YF55 - 144 Transceivers

(55 x 55 mm2)

TX 400 384, 0, 144, 24, 0 - - -
TX 850 - 440, 8, 216, 24, 24 440, 8, 216, 48, 24 -
TX 1100 - 440, 8, 216, 24, 24 440, 8, 216, 48, 24 -
TX 1650 - - 440, 8, 216, 72, 24 -
TX 2100 - - 440, 8, 216, 72, 24 -
TX 2500 - - 440, 8, 216, 72, 24 296, 8, 144, 120, 24
TX 2800 - - 440, 8, 216, 72, 24 296, 8, 144, 120, 24

Figure 3. Tile Configuration 1: HF35 Package
Figure 4. Tile Configuration 2: NF43 Package
Figure 5. Tile Configuration 3: SF50 Package
Figure 6. Tile Configuration 4: UF50 Package
Figure 7. Tile Configuration 5: YF55 Package
1 The number of 27x27 multipliers is one-half the number of 18x19 multipliers.
2 All packages are ball grid arrays with 1.0 mm pitch.
3 High-Voltage I/O pins are used for 3 V and 2.5 V interfacing.
4 Each LVDS pair can be configured as either a differential input or a differential output.
5 High-Voltage I/O pins and LVDS pairs are included in the General Purpose I/O count. Transceivers are counted separately.
6 Each package column offers pin migration (common circuit board footprint) for all devices in the column.
Level Two Title