Intel® Stratix® 10 TX Device Overview

ID 683717
Date 8/18/2022
Public
Document Table of Contents

1.17. Internal Embedded Memory

Intel® Stratix® 10 TX devices contain three types of embedded memory blocks: eSRAM (47.25 Mbit) in select devices, M20K (20 Kb), and MLAB (640 bit). This variety of on-chip memory provides fast access times and low latency for applications such as wide and deep FIFOs and variable buffers.

The eSRAM blocks are a new innovation in Intel® Stratix® 10 TX devices. These large embedded SRAM blocks are tightly coupled to the core fabric and are directly accessible with no need for a separate memory controller. Each eSRAM block is arranged as 8 channels, 40 banks per channel, with a total capacity of 47.25 Mbits running at clock rates up to 750 MHz. Within the eSRAM block, each channel has a bus width of 72 bit read and 72 bit write, and has one READ and one WRITE per channel. This allows each eSRAM block to support a total aggregate bandwidth (read + write) of up to 864 Gbps.

The eSRAM block is implemented as a simple dual port memory with concurrent read and write access per channel, and includes integrated hard ECC generation and checking. Compared to an off-chip SRAM solution, the eSRAM block allows you to reduce system power and save board space and cost.

The M20K and MLAB blocks are familiar block sizes carried over from previous Intel device families. The MLAB blocks are ideal for wide and shallow memories, while the M20K blocks are intended to support larger memory configurations and include hard ECC. Both M20K and MLAB embedded memory blocks can be configured as a single-port or dual-port RAM, FIFO, ROM, or shift register. These memory blocks are highly flexible and support a number of memory configurations as shown in the following table.

Table 10.  Internal Embedded Memory Block Configurations

MLAB (640 bits)

M20K (20 Kb)

64 x 10 (supported through emulation)

32 x 20

2K x 10 (or x8)

1K x 20 (or x16)

512 x 40 (or x32)

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