Stratix® 10 TX Device Overview

Download PDF
ID 683717
Date 9/07/2023
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Stratix® 10 TX Device Overview
1. Intel® Stratix® 10 TX Device Overview x
1.1. Intel® Stratix® 10 TX Devices 1.2. Innovations in Intel® Stratix® 10 TX Devices 1.3. Intel® Stratix® 10 TX Features Summary 1.4. Intel® Stratix® 10 TX Block Diagram 1.5. Intel® Stratix® 10 TX Family Plan 1.6. Intel® Hyperflex™ Core Architecture 1.7. Heterogeneous 3D SiP Transceiver Tiles 1.8. Intel® Stratix® 10 TX Transceivers 1.9. PCI Express Gen1/Gen2/Gen3 Hard IP 1.10. Ethernet MAC, Reed-Solomon FEC for NRZ signals (528, 514) and PAM4 signals (544, 514) 1.11. 10G Ethernet Hard IP 1.12. Interlaken PCS Hard IP 1.13. External Memory and General Purpose I/O 1.14. Adaptive Logic Module (ALM) 1.15. Core Clocking 1.16. Fractional Synthesis PLLs and I/O PLLs 1.17. Internal Embedded Memory 1.18. Variable Precision DSP Block 1.19. Hard Processor System (HPS) 1.20. Power Management 1.21. Device Configuration and Secure Device Manager (SDM) 1.22. Device Security 1.23. Configuration via Protocol Using PCI Express* 1.24. Partial and Dynamic Reconfiguration 1.25. Fast Forward Compile 1.26. Single Event Upset (SEU) Error Detection and Correction 1.27. Document Revision History for the Intel® Stratix® 10 TX Device Overview
1.1. Intel® Stratix® 10 TX Devices x
1.1.1. Available Options
1.8. Intel® Stratix® 10 TX Transceivers x
1.8.1. PMA Features 1.8.2. PCS Features
1.19. Hard Processor System (HPS) x
1.19.1. Key Features of the Intel® Stratix® 10 HPS
1. Intel® Stratix® 10 TX Device Overview

1.27. Document Revision History for the Intel® Stratix® 10 TX Device Overview

Version Changes
2023.09.07 Removed Ethernet AVB from the list of Ethernet standards that the HPS supports.
2022.08.18 Made the following change:
  • Removed the details of Register state readback and writeback feature from Key Features of Intel Stratix 10 TX Devices Compared to Stratix V Devices table.
  • Removed readback and writeback feature from advantages in Device Configuration and Secure Device Manager (SDM) section.
2020.09.28 Made the following change:
  • Added black key provisioning (-BK) devices. See the "Sample Ordering Code" figure in Available Options.
2020.03.24 Made the following change:
  • Added advanced security (-AS) devices.
2019.08.19 Made the following changes:
  • Added composition details for the leaded and lead-free contact device options.
  • Updated family plan device options and added a tile layout variant.
2019.03.11 Made the following changes:
  • Updated maximum transceiver data rate from 30 Gbps to 28.9 Gbps.
2019.02.15 Made the following changes:
  • Added "Figure 1: Sample Ordering Code and Available Options for Intel® Stratix® 10 Devices" in the " Intel® Stratix® 10 TX Devices" section.
  • Changed the number of eSRAM memory block to 47.25 Mb and the number of embedded memory to 94.5 Mb.
  • Changed the number of maximum transceiver data rate to 57.8 Gbps.
  • Added the resource availabilities for the TX 400, TX 650, TX 850, and TX 1100 devices in the "Intel Stratix 10 TX Family Plan—FPGA Core (part 1)" table.
  • Added the resource availabilities for the TX 400, TX 650, TX 850, and TX 1100 devices in the "Intel Stratix 10 TX Family Plan - Interconnects, PLLs and Hard IP (part 1)" table.
  • Added the resource availabilities for the TX 400, TX 650, TX 850, and TX 1100 devices in the "Intel Stratix 10 TX Package Plan" table.
  • Updated Tile Layout diagrams for NF43 (F1760) and SF50 (F2397) packages.
2018.08.10 Made the following changes:
  • Changed the direction arrow from the coefficient registers block in the "DSP Block: High Precision Fixed Point Mode" figure.
  • Changed the descriptions for the core process technology and power management features in the " Intel® Stratix® 10 TX Device Features" table.
  • Changed the description of the SmartVID in the "Power Management" section.
2018.02.21 Made the following changes:
  • Updated the fPLL counts in the " Intel® Stratix® 10 TX Family Plan - Interconnects, PLLs and Hard IP (part 2)" table.
  • Changed the fPLL counts in the "Fractional Synthesis and I/O PLLs" section.
2017.10.30 Made the following changes:
  • Changed the resource availabilities for the TX 1650 and TX 2100 devices in the " Intel® Stratix® 10 TX Family Plan—FPGA Core (part 1)" table.
2017.08.02 Made the following changes:
  • Only some of the devices have eSRAM. Mentioned this in the appropriate places in the app note
  • 100Gbe Hard IP included in the bottom left H-tile of the Intel® Stratix® 10 TX Architecture Block Diagram
  • Added a new column "HPS" in the Intel® Stratix® 10 TX Family Plan - FPGA Core (part 1) table
  • Updated table " Intel® Stratix® 10 TX Family Plan - Interconnects, PLLs and Hard IP (part 2)"
  • Added Tile Layout diagrams
2016.10.31 Initial release.
Level Two Title