Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

ID 683704
Date 9/26/2022

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4.1.2. PCIe* Wake-Up Time Requirement

For an open system, you must ensure that the PCIe* link meets the PCIe* wake-up time requirement as defined in the PCI Express* CARD Electromechanical Specification. The transition from power-on to the link active (L0) state for the PCIe* wake-up timing specification must be within 200 ms. The timing from FPGA power-up until the Hard IP for PCI Express* IP Core in the FPGA is ready for link training must be within 120 ms.