Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide
ID
683704
Date
9/26/2022
Public
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1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10
7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History
5.3.1. Vendor Specific Capability Header Register
5.3.2. Vendor Specific Header Register
5.3.3. Intel Marker Register
5.3.4. User Configurable Device/Board ID Register
5.3.5. CvP Status Register
5.3.6. CvP Mode Control Register
5.3.7. CvP Data Registers
5.3.8. CvP Programming Control Register
5.3.9. CvP Credit Register
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5.3.9. CvP Credit Register
The credit registers slow down the transmission of the CvP data to handle back pressure when there is no buffer space available within the configuration system. The crediting mechanism handles the back pressure from the configuration system. The total credits register increments each time an additional 4k buffer is available.
Bits | Reset Value | Access | Description |
---|---|---|---|
[31:16] | 0x00 | RO | Reserved. |
[15:8] | 0x00 | RO | Least significant 8 bits of the total number of 4k credits granted. |
[7:0] | 0x00 | RO | Reserved. |