Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

Download PDF
ID 683704
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations and Restrictions
1.3.1. CvP Limitations and Restrictions x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe* Wake-Up Time Requirement
4.1.2. PCIe* Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing the Upstream Open Source CvP Driver in Linux Systems 6.1.5.2. Modifying MSEL/DIP switch on Intel® Stratix® 10 FPGA Development Kit 6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe* Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting up the Base Revision 6.2.4. Setting up and Compile the Updated Revision 6.2.5. Converting the SOF file of the Updated Revision 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe Link
6.2.3. Setting up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10
7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History

8. Document Revision History

Table 16.  Document Revision History for Intel® Stratix® 10 Configuration via Protocol Implementation User Guide
Document Version Intel® Quartus® Prime Version Changes
2022.09.26 22.2 Added second note under image in the Implementation of CvP Update Mode section.
2022.08.05 22.2
  • Made changes to the following sections to remove downstream driver support.
    • CvP Driver Support
    • Installing the Upstream Open Source CvP Driver on Linux Systems
    • Programming CvP Images
    • Implementation of CvP Update Mode
    • Programming the Core RBF file from the Updated Revision via PCIe Link
  • Added .sof file conditions to CvP Limitations and Restrictions.
2021.07.01 21.2
Sections Updated:
2021.02.19 19.3
Sections updated:
  • CvP Modes
  • CvP System
  • Configuration Images
2020.09.22 19.3
  • Removed support for Avalon® Streaming (Avalon-ST) x8 configuration scheme.
  • Added a note in section CvP Systems to clarify the location of the PCIe* Hard IP block.
  • Added information about the supported tile in Table: CvP Support for Intel® Stratix® 10 Device Family.
2020.05.19 19.3 Corrected the file selection for AVST configuration mode in the following sections:
  • Converting the SOF File
  • Converting the SOF file of the Updated Revision
2020.01.10 19.3 Updated Figure: PCIe Timing Sequence in CvP Initialization Mode to include GPIO status.
2019.12.16 19.3
  • Added a link to the Intel Stratix 10 CvP Update Reference Design.
  • Updated following links:
    • CvP driver link
    • Intel Stratix 10 CvP Initialization Reference Design
  • Modified the steps in the following sections:
    • Creating a Reserved Core Partition
    • Setting up and Compile the Updated Revision
  • Added information about checking the .qsf file settings in Defining a Logic Lock Region section.
  • Modified step tp program the core.rbf file in section Programming the FPGA using the Base Revision Image.
2019.09.30 19.3
  • Added support for Avalon® Streaming x8 configuration scheme.
  • Replaced the Convert Programming File (CPF) tool related information with Programming File Generator (PFG) in the following sections:
    • Converting the SOF File
    • Converting the SOF File of the Updated Revision
2019.07.26 18.1
  • Corrected the byte offset for the CvP Programming Control Register.
  • Corrected register name in Figure 7: CvP Driver Flow.
2019.06.20 18.1 Clarified how to program the FPGA for CvP update mode.
2019.01.17 18.1
  • Modified the following in Setting up the Base Revision section:
    • Figure: Creating Design Partition from Project Navigator
    • Figure: Design Partitions Window
    • Figure: Creating Logic Lock Region from Project Navigator
  • Added Figure: Design Partitions Window in section Setting up and Compile the Updated Revision section.
2018.11.29 18.1 Modified the following diagrams:
  • Figure: Single Endpoint Topology
  • Figure: Multiple Endpoints Topology
2018.09.24 18.1
  • CvP update mode is now supported in the current version of the Intel® Quartus® Prime Pro Edition software.
  • Added new section Implementation of CvP Update Mode.
  • Modified diagrams:
    • Figure: Periphery and Core Image Storage Arrangement for CvP Core Image Update
    • Figure: Single Endpoint Topology
    • Figure: Multiple Endpoints Topology
  • Updated Figure: CvP Driver Flow in section CvP Driver Flow.
  • CVP_DATA2 register is no longer functional in Intel® Stratix® 10 devices.
  • Added new sections:
    • CvP Limitations and Restrictions
    • CvP Error Recovery
    • Intel Stratix 10 Configuration via Protocol (CvP) Implementation User Guide Archives
2018.07.17 18.0
  • Added a note in CvP Modes section to clarify CvP update mode support in the current version of the Intel® Quartus® Prime Pro Edition software.
  • Modified Figure: PCIe Timing Sequence in CvP Initialization Mode diagram.
2018.06.18 18.0
  • Corrected the periphery image and core image definitions in Configuration Images section.
  • Added Figure: PCIe Timing Sequence in CvP Initialization Mode diagram and Table: Power-up Sequence Timing in CvP Initialization Mode information for CvP initialization.
  • Modified Figure: Single Endpoint Topology and Figure: Multiple Endpoint Topology in CvP Topologies chapter.
  • Added a note to clarify the Linux driver support provided by Intel® .
  • Updated the Figure: CvP Driver Flow.
  • Corrected the VSEC registers for CvP in VSEC Registers for CvP section.
  • Minor updates in Implementation of CvP Initialization Mode section.
Date Version Changes
December 2017 2017.12.18 Initial release.
Level Two Title