Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide

Download PDF
ID 683704
Date 9/26/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations and Restrictions
1.3.1. CvP Limitations and Restrictions x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe* Wake-Up Time Requirement
4.1.2. PCIe* Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
5. CvP Driver and Registers x
5.1. CvP Driver Support 5.2. CvP Driver Flow 5.3. VSEC Registers for CvP
5.3. VSEC Registers for CvP x
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10 x
6.1. Implementation of CvP Initialization Mode 6.2. Implementation of CvP Update Mode
6.1. Implementation of CvP Initialization Mode x
6.1.1. Generating the Synthesis HDL files for Avalon® -ST Intel® Stratix® 10 Hard IP for PCI Express 6.1.2. Setting up the CvP Parameters in Device and Pin Options 6.1.3. Compiling the Design 6.1.4. Converting the SOF File 6.1.5. Bringing up the Hardware
6.1.5. Bringing up the Hardware x
6.1.5.1. Installing the Upstream Open Source CvP Driver in Linux Systems 6.1.5.2. Modifying MSEL/DIP switch on Intel® Stratix® 10 FPGA Development Kit 6.1.5.3. Programming CvP Images
6.2. Implementation of CvP Update Mode x
6.2.1. Instantiating the PCIe* Hard IP 6.2.2. Setting Up the CvP Parameters 6.2.3. Setting up the Base Revision 6.2.4. Setting up and Compile the Updated Revision 6.2.5. Converting the SOF file of the Updated Revision 6.2.6. Programming the Core RBF file from the Updated Revision via PCIe Link
6.2.3. Setting up the Base Revision x
6.2.3.1. Creating a Reserved Core Partition 6.2.3.2. Defining a Logic Lock Region 6.2.3.3. Compiling and Exporting the Root Partition
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization and Update Mode in Intel® Stratix® 10
7. Intel® Stratix® 10 Configuration via Protocol (CvP) Implementation User Guide Archives
8. Document Revision History

5.3.1. Vendor Specific Capability Header Register

Table 6.  Vendor Specific Capability Header Register (Byte Offset: 0xB80)
Bits Name Reset Value Access Description
[15:0] PCI Express* Extended Capability ID 0x000B RO PCIe* specification defined value for VSEC Capability ID.
[19:16] Version 0x1 RO PCIe* specification defined value for VSEC version.
[31:20] Next Capability Offset Variable RO Starting address of the next Capability Structure implemented, if any.
Level Two Title