eCPRI Intel® FPGA IP User Guide

ID 683685
Date 8/03/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6. IP Registers

The eCPRI IP core registers are 32-bits wide and are accessible using the Avalon® memory-mapped interface. This table lists the registers available in the IP core. All unlisted locations are reserved.
Table 54.  Register Access Codes
Code Description
RW Read and write
RO Read only
RW1C Read, write, and clear. The user application writes 1 to the register bit(s) to invoke a defined instruction. The IP core clears the bit(s) upon executing instructions.