eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 8/03/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. IP Parameters 4. Functional Description 5. Interface Overview 6. IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for eCPRI Intel® FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. Introduction
2. Getting Started
3. IP Parameters
4. Functional Description
5. Interface Overview
6. IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for eCPRI Intel® FPGA IP User Guide

5.2. Power, Reset, and Firewalls Signals

Table 27.  eCPRI IP Reset, Power, and Firewalls SignalsThese signals are asynchronous.
Signal Name Width (Bits) I/O Direction Description
rst_rx_n 1 Input Reset signal from Ethernet MAC RX.

Resets the eCPRI IP in RX direction. Resets the De-concatenation, Header de-mapper, Ethernet header removal, eCPRI message 5 packet parser and, Packet classifier.

rst_tx_n 1 Input Reset signal from Ethernet MAC TX.

Resets the eCPRI IP in TX direction. Resets the Concatenation, Header mapper, Ethernet header insertion, eCPRI message 5 packet parser, and Packet queue.

rst_csr_n 1 Input Reset signal for CSR logic.

Resets the eCPRI IP control and status registers. When asserted, resets the eCPRI IP.

tx_lanes_stable 1 Input Signal that indicates the clk_tx signal from MAC is stable and ready for operation.
rx_pcs_ready 1 Input Signal that indicates the clk_rx signal from MAC is stable and ready for operation.
iwf_rst_tx_n 1 Input Reset signal for the IWF TX path.
iwf_rst_rx_n 1 Input Reset signal for the IWF RX path.
rst_tx_n_sync 1 Output

Reset output from IWF. This signal is synchronous to clk_tx.

Intel recommends you to connect this signal to iwf_rst_tx_n.
rst_rx_n_sync 1 Output

Reset output from IWF. This signal is synchronous to clk_rx.

Intel recommends you to connect this signal to iwf_rst_rx_n.
iwf_gmii_rxreset_n[N] 1 Input Resets the GMII receiver interface and FIFO read logic.
iwf_gmii_txreset_n[N] 1 Input Resets the GMII transmitter interface and FIFO write logic.
gmii_rxreset_n[N] 1 Output Resets the GMII receiver interface and FIFO read logic.
gmii_txreset_n[N] 1 Output Resets the GMII transmitter interface and FIFO write logic.

Section Content
Reset Control and Initialization Flows

Level Two Title