eCPRI Intel® FPGA IP User Guide

ID 683685
Date 8/03/2023
Public

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5.10. External ST Sink Interface

Table 38.  Signals of the External ST Sink InterfaceThis table lists the ports from external user logic to L2/L3 parser. All signals are synchronous to ext_sink_clk.
Signal Name Width (Bits) I/O Direction Description
ext_sink_valid 1 Input Avalon® sink valid from external user logic to L2/L3 parser.
ext_sink_data DATA_WIDTH 7 Input Avalon® sink write data from external user logic to L2/L3 parser.
ext_sink_sop 1 Input Avalon® sink start of packet from external user logic to L2/L3 parser. Indicates the beginning of packet.
ext_sink_eop 1 Input Avalon® sink end of packet from external user logic to L2/L3 parser. Indicates the end of packet.
ext_sink_empty LOG2(DATA_WIDTH7/8) Input Avalon® sink empty from external user logic to L2/L3 parser. Indicates the number of symbols that are empty, that is, do not represent valid data.
ext_sink_ready 1 Output Avalon® sink ready driven from L2/L3 parser. Indicate L2/L3 parser can accept data.
ext_sink_error 1 Input Avalon® sink error from external user logic to L2/L3 parser. A bit mask to mark errors affecting the data being transferred in the current cycle.
ext_ptp_timestamp_request_fingerprint 7 Input Provides the fingerprint of the V2-format 1588 PTP frame currently beginning transmission on the Ethernet link.

Value is valid when the ext_sink_sop signal is asserted.

The encoding format is:
  • Bit [6:0]: PTP Fingerprint ID
ext_tx_egress_timestamp_96b_data 96 Output Provides the V2-format timestamp when a 1588 PTP frame begins transmission on the Ethernet link. Value is valid when the tx_egress_timestamp_96b_valid signal is asserted.
ext_tx_egress_timestamp_96b_valid 1 Output Indicates that the ext_tx_egress_timestamp_96b_data signals are valid in the current ext_sink_clk clock cycle. This signal is valid only in two-step clock mode.
ext_tx_egress_timestamp_96b_fingerprint 7 Output Fingerprint signal for current TX packet.

Assigns an PTP_TS_FP_WIDTH fingerprint to a TX packet that is being transmitted, so that the two-step or one-step PTP/eCPRI one-way delay measurement timestamp associated with the TX packet can be identified. The timestamp returns with the same fingerprint.

Valid only when the TX valid and TX SOP signals are asserted.

The encoding format is:
  • Bit [6:0]: PTP Fingerprint ID
ext_tx_ingress_timestamp_96b_data 96 Input Provides the V2-format timestamp when a 1588 PTP frame begins transmission on the Ethernet link.

Value is valid when the ext_sink_sop signal is asserted.

ptp_tx_ingress_timestamp_96b_data 96 Output Provides the V2-format timestamp when a 1588 PTP frame begins transmission on the Ethernet link.

Synchronous with mac_source_valid signal.

7 This is set to 64. This parameter is hidden from user and you can't change it.