eCPRI Intel® FPGA IP User Guide

ID 683685
Date 8/03/2023
Public

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5.15.9. CPRI Gigabit Media Independent Interface (GMII)

Table 52.  Signals of CPRI GMII Interface
Signal Name Width (Bits) I/O Direction Description
TX Interface
gmii_txen[N] 1 Output Valid signal for GMII interface that indicate data is valid. This signal required to be asserted two clock cycles earlier for the character S to be inserted into the data stream as the start of packet before takes in the real GMII data. The deassertion of this signal trigger the assertion of /T/R as the representation of end of packet.

This signal is going to CPRI MAC interface.

gmii_txer[N] 1 Output Ethernet transmit coding error. When this signal is asserted, char /V/ will be inserted and pass into the CPRI link.

This signal is going to CPRI MAC interface.

gmii_txd[N] 8 Output Ethernet transmit data. The data transmitted from the external Ethernet block to the CPRI IP core, for transmission on the CPRI link. This input bus is synchronous to the rising edge of gmii_txclk clock.

This signal is going to CPRI MAC interface.

gmii_txfifo_status[N] 4 Input Ethernet TX PCS FIFO fill level status. The individual bits have the following meanings:
  • Bit [3[: FIFO empty
  • Bit [2]: FIFO almost empty
  • Bit [1]: FIFO full
  • Bit [0]: FIFO almost full
This signal is going to CPRI MAC interface.
RX Interface
gmii_rxdv[N] 1 Input

Ethernet receive data valid. Indicates the presence of valid data or initial start-of-packet control character on gmii_rxd.

This signal is going to CPRI MAC interface.

gmii_rxer[N] 1 Input

Ethernet receive error. Indicates an error on gmii_rxd. When this signal is asserted, the value on gmii_rxd is 0x0E.

This signal is going to CPRI MAC interface.

gmii_rxd[N] 8 Input

Ethernet receive data. Data bus for data from the CPRI IP to the external Ethernet block. All bits are deasserted during reset, and all bits are asserted after reset until the CPRI IP achieves frame synchronization.

This signal is going to CPRI MAC interface.

gmii_rxfifo_status[N] 4 Input Ethernet RX PCS FIFO fill level status. The individual bits have the following meanings:
  • Bit [3[: FIFO empty
  • Bit [2]: FIFO almost empty
  • Bit [1]: FIFO full
  • Bit [0]: FIFO almost full
This signal is going to CPRI MAC interface.