eCPRI Intel® FPGA IP User Guide

ID 683685
Date 8/03/2023

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Document Table of Contents

5.6. Configuration Avalon® Memory-Mapped Interface

Table 31.  Signals of the Configuration Avalon® Memory-Mapped Interface This section lists ports that provides access to internal control and status registers of the eCPRI IP. All signals are synchronous to clk_csr.
Signal Name Width (Bits) I/O Direction Description
csr_address 16 Input Configuration register address.
csr_write 1 Input Configuration register write enable.
csr_writedata 32 Input Configuration register write data.
csr_read 1 Input Configuration register read enable.
csr_readdata 32 Output Configuration register read data.
csr_writerequest 1 Output Configuration register write request.
csr_readdatavalid 1 Output Configuration register read data valid.