AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor

ID 683661
Date 2/21/2017
Document Table of Contents Nios II Gen2 Processor

The Nios II Gen2 Processor in the reference design has the following functions:

  • A bus master which handles all interface operations with the Altera On-Chip Flash IP core including read, write, and erase.
  • Provides an algorithm in software to receive the programming bit stream from a host computer and trigger reconfiguration through the Dual Configuration IP core.

You need to set the reset vector of the processor accordingly. This is to ensure the processor boots the correct application code from either UFM or external QSPI flash.

Note: If the Nios II application code is large, Intel recommends that you store the application code in the external QSPI flash. In this reference design, the reset vector is pointing to the external QSPI flash where the Nios II application code is stored.