AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor

ID 683661
Date 2/21/2017
Document Table of Contents Altera UART IP Core

The UART IP core allows the communication of serial character streams between an embedded system in MAX 10 FPGA and an external device. As an Avalon-MM master, the Nios II processor communicates with the UART IP core, which is an Avalon-MM slave. This communication is done by reading and writing control and data registers.

The core implements the RS-232 protocol timing and provides the following features:

  • adjustable baud rate, parity, stop, and data bits
  • optional RTS/CTS flow control signals