AN 741: Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor

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ID 683661
Date 2/21/2017
Public
Document Table of Contents
Document Table of Contents x
1. Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor
1. Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor x
1.1. Remote System Upgrade with MAX 10 FPGA Overview 1.2. Abbreviations 1.3. Prerequisite 1.4. Requirements 1.5. Reference Design Files 1.6. Reference Design Functional Description 1.7. Reference Design Walkthrough 1.8. Document Revision History
1.6. Reference Design Functional Description x
1.6.1. Reference Design IP Core Components 1.6.2. The Nios II EDS Software Application Design
1.6.1. Reference Design IP Core Components x
1.6.1.1. Nios II Gen2 Processor 1.6.1.2. Altera On-Chip Flash IP Core 1.6.1.3. Altera Dual Configuration IP Core 1.6.1.4. Altera UART IP Core 1.6.1.5. Generic Quad SPI Controller IP Core
1.6.2. The Nios II EDS Software Application Design x
1.6.2.1. Updating Application Images Remotely 1.6.2.2. Triggering Reconfiguration Remotely
1.7. Reference Design Walkthrough x
1.7.1. Generating Programming Files 1.7.2. Programming the QSPI 1.7.3. Programming the FPGA with Initial Image using JTAG 1.7.4. Updating Image and Triggering Reconfiguration using UART
1.7.1. Generating Programming Files x
1.7.1.1. Generating files for QSPI Programming 1.7.1.2. Generating files for Remote System Upgrade
1.7.1.2. Generating files for Remote System Upgrade x
1.7.1.2.1. .pof Generation through Convert Programming Files
1. Remote System Upgrade for MAX 10 FPGA Devices over UART with the Nios II Processor

1.5. Reference Design Files

Table 2.  Design Files Included in the Reference Design
File Name Description
Factory_image
  • Quartus II hardware design file to be stored in CFM0.
  • The fallback image/factory image to be used when error occurs in the application image download.
app_image_1
  • Quartus II hardware design file to be stored in CFM1 and CFM2.1
  • The initial application image loaded in the device.
app_image_2 Quartus II hardware design file that replaces app_image_2 during remote system upgrade.
Remote_system_upgrade.c Nios II software application code acting as the controller for the remote upgrade system design.
Remote Terminal.exe
  • Executable file with a GUI.
  • Functions as the terminal for host to interact with MAX 10 FPGA development kit.
  • Sends programming data through UART.
  • Source code for this terminal is included.
Table 3.  Master Files Included in the Reference Design

You can use these master files for the reference design without compiling the design files.

File Name Description

factory_application1.pof

factory_application1.rpd

Quartus II programming file that consists of factory image and application image 1, to be programmed into CFM0 and CFM1 & CFM2 respectively at initial stage.

factory_application2.pof

factory_application2.rpd

  • Quartus II programming file that consists of factory image and application image 2.
  • Application image 2 will be extracted later to replace application image 1 during remote system upgrade, named application_image_2.rpd below.
application_image_1.rpd Quartus II raw programming data file that contain application image 1 only.
application_image_2.rpd Quartus II raw programming data file that contains application image 2 only.
Nios_application.pof
  • Programming file that consists Nios II processor software application .hex file only.
  • To be programmed into external QSPI flash.
pfl.sof
  • Quartus II .sof containing PFL.
  • Programmed into QSPI flash on MAX 10 FPGA Development kit.
1 In dual configuration images configuration mode, CFM1 and CFM2 are combined to a single CFM storage.
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