Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 1/07/2022

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Document Table of Contents Report Pipelining Information

The Timing Analyzer's Reports > Design Metrics > Report Pipelining Information... command allows you to generate a report that can help you to identify potential areas of over-pipelining in your design. Excessive pipelining unnecessarily consumes area. The equivalent scripting command is report_pipelining_info.

Report Pipelining Information... does not perform any functional analysis in making the recommended pipeline stage adjustment. You must be aware of any potential functional changes from removing pipeline stages. There may be circumstances when all the stages in a register pipeline are necessary for functional reasons. The report helps to identify location with more registers than necessary for covering distance.

Figure 39. Report Pipelining Information Report
Figure 40. Report Detailed Pipelining

The detailed report shows every register in a tree structure. Over- or under-pipelining recommendations are in the main report. The following shows every single register inside the bus chain in a tree structure:

Figure 41. Detailed Pipelining Result

To help identify potential over-pipelining, Report Pipelining Information reports:

  • The recommended pipeline stage adjustment across bus
  • The minimum total slack of one bit across bus
  • The minimum average slack of one bit across bus
  • The distance between the registers
  • The width of buses in your design
  • The number of sequential registers
  • The number of registers on the bus

The Recommended Pipeline Stage Adjustment Across Bus reports the number of registers that you can remove from the bus for each bit. The Average Distance Per Stage, Max Distance Per Stage, and Min Distance Per Stage columns report the Manhattan distance measured in logic array blocks (LABs). The Bus Average Depth, Bus Max Depth, and Bus Min Depth columns report the number of sequential, single fan-out registers. For registers that have more than one clock source, the report lists the fastest one.

The 1+ sign under Recommended Pipeline Stage Adjustment Across Bus column means that the bus might need to add more registers to meet timing requirement. Refer to the Fast Forward Timing Closure Recommendations report.

If the report identifies a large register chain with multiple sequential registers, and the distance between registers is low, that condition can suggest over-pipelining. You may be able to remove some registers to recover some of the device area and reduce congestion.

The following options are available for this report:

Figure 42. Report Pipelining Information Dialog Box
Table 21.  Report Pipelining Information Settings
Option Available Settings
Pipeline Specifies the thresholds for reporting a register pipeline. You can define the Minimum average bus depth, the Minimum bus width, and the Maximum number of rows that the report includes.
Report panel name Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name, you can Overwrite or Append the file with latest data.
Tcl command Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file.