Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 1/07/2022

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Document Table of Contents

2.4.1. Design Visualization Tools

The Intel® Quartus® Prime software provides tools that display different graphical representations of your design to help you visualize and optimize placement, connectivity, and routing congestion at various stages of the design cycle.

Table 2.  Design Visualization Tools
Tool Description
Snapshot Viewer The Compiler can preserve the results of each compilation stage as a snapshot for analysis optimization at each stage. The Snapshot Viewer allows you to easily analyze and optimize compilation results for a snapshot. The Snapshot Viewer provides centralized access to functions and tools that allow you to rapidly analyze clocking, congestion, and correct failing paths and high fan-out nets.
RTL Viewer Provides a schematic representation of the design before synthesis and place-and-route.
Technology Map Viewer Provides a schematic representation of the design implementation in the selected device architecture after synthesis and place-and-route. Optionally, you can include timing information.
Chip Planner Allows you to make floorplan assignments, perform power analysis, and visualize critical paths and routing congestion. Click the Report Routing Utilization task to display the routing resource congestion.
Interface Planner Simplifies the planning of accurate constraints for physical implementation. Use Interface Planner to prototype interface implementations, plan clocks, and rapidly define a legal device floorplan.
Design Partition Planner Displays design entities, I/O banks, connectivity, design hierarchy, and design partition membership. Design Partition Planner can assist you in visualizing a design's structure for creating effective design partitions.
Design Partition Planner and Chip Planner Allows you to partition and layout the design at a higher level chip view.