Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 1/07/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

6.5.3.4. Report Register Spread

The Timing Analyzer's Reports > Design Metrics > Report Register Spread... command analyzes the final placement to identify registers with sinks pulling them in various directions. These registers are potential candidates for duplication. The equivalent scripting command is report_register_spread.

Registers that drive in opposite directions and connect to high fan-out can have placement-warping effects on the floorplan that impact fMAX. The placement-warping may not cause timing failures. Therefore, you can view this report to identify such registers. Taking steps to address the registers listed in the report can make placement of the design easier and improve fMAX performance.

You can automate duplication of registers with the DUPLICATE_REGISTER and DUPLICATE_HIERARCHY_DEPTH .qsf assignments, or you can manually modify RTL to duplicate registers or refactor logic. Refer to "Automatic Register Duplication: Hierarchical Proximity" in Intel Quartus Prime Pro Edition User Guide: Design Optimization.

Figure 33. Report Register Spread Report

You can specify various options to customize the report.

Table 19.  Report Register Spread Settings
Option Available Settings
Spread Type Specifies the type of spread data in the report:
  • Tension—reports the sum over each sink of the distance from it to the centroid of all the sinks.
  • Angle—reports how far around the source register the fan-outs wrap, expressed from 0 to 360 degrees. This value corresponds to 360 minus the maximum angle between any two angularly adjacent sinks. This metric complements Tension by identifying registers which are surrounded by their sinks in all directions, and not those registers only being pulled in a few directions.
  • Span—reports the maximum 1-dimensional delta between the left bottom-most sink and the right top-most sink.
  • Area—reports the coverage of the sinks by number of LABs on the FPGA device. This option multiplies the span of the sinks in both X- and Y- dimensions. This metric complements Span by incorporating both dimensional spans of the sinks, and not only the maximum sink.
  • Count—reports registers with the largest sink counts.
Sink Type Specifies the type of sink in the report:
  • Endpoint—the nodes (usually registers) that terminate timing paths from a register.
  • Immediate Fanout—the immediately connected nodes of the register. For example, lookup tables, other registers, RAM, or DSP blocks.
From Clock Filters paths in the report to show only the launching clocks you specify.
To Clock Filters paths in the report to show only the latching clocks you specify, allowing you to debug one clock at a time.
Report number of registers Specifies the number of registers to display in the report. The default value for Report number of registers is 10.
Report panel name Specifies the name of the report panel. You can optionally enable File name to write the information to a file. If you append .htm or .html as a suffix, the Timing Analyzer produces the report as HTML. If you enable File name, you can Overwrite or Append the file with latest data.
Tcl command Displays the Tcl syntax that corresponds with the GUI options you select. You can copy the command from the Console into a Tcl file.
Figure 34. Report Register Spread Types
Figure 35. Report Register Spread Dialog Box