Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 1/07/2022

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7.3. Using Logic Lock Regions in the Chip Planner

You can easily create Logic Lock regions in the Chip Planner and assign resources to them. Design Assistant can help you to identify any improperly configured Logic Lock region constraints in your design.

To detect and resolve any issues with Logic Lock regions in your project, click Report DRC to run the Design Assistant to check for the FLP rule category. FLP Design Assistant rules detect possible issues with logic lock regions.