Intel® Quartus® Prime Pro Edition User Guide: Design Optimization

ID 683641
Date 1/07/2022

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Document Table of Contents Example: Placement Best Practices for Intel® Arria® 10 FPGAs

Logic Lock regions must take into account the device topology.
Note: As a best practice, define resource placement with iterative design flows. Use techniques like the Early Place Flow to guide your floorplanning decisions before setting hard placement constraints.

This example describes how I/O Columns constrain locations in Logic Lock regions in designs targeting Intel® Arria® 10 FPGAs.

Figure 85. I/O Columns in Intel® Arria® 10 FPGAs Intel® Arria® 10 FPGAs have I/O columns located in the middle of the device. Signals can only enter or exit these columns from the side that faces the device edge.
Figure 86. Signals Crossing I/O Columns in Intel® Arria® 10 FPGAsRouting a signal to cross the I/O column increases the routing delay, and can reduce design performance.
Figure 87.  Strategic Placement for Logic Lock Regions in Intel® Arria® 10 FPGAs
  • If a Logic Lock region contains a register that interface with the I/O column, place the Logic Lock region so that the region covers the I/O column and the core logic, for better access to the I/O column adjacent to the outer column edge.
  • For high speed signal, you can get best results if you place the Logic Lock region on the outside of the I/O column, because the fitter is less likely to cross the column and incur delay.