Nios® V Processor Reference Manual

ID 683632
Date 11/15/2021
Public

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2.1. Processor Performance Benchmarks

Table 1.  fmax (MHz)
Device Family Nios® V/m Processor
Intel® Cyclone® 10 270.27
Intel® Arria® 10 305.62
Intel® Stratix® 10 361.93
Intel® Agilex™ 566.25
Table 2.  Logic Size
Device Family Nios® V/m Processor
Intel® Cyclone® 10 1375
Intel® Arria® 10 1375
Intel® Stratix® 10 1580
Intel® Agilex™ 1509
Table 3.  Architecture Performance
Performance Metric Nios® V/m Processor
DMIPS/MHz Ratio 0.464
CoreMark/MHz Ratio 0.32148
Intel uses the following options for this benchmark:
  • Maximum performance result based on 10 Seed Sweep from Intel® Quartus® Prime Design Suite software version 21.3.
  • Fastest speed grade from each device family.
  • Peripherals:
    • Nios® V/m processor core
    • 4KB On-Chip Memory for Instruction Bus
    • 4KB On-Chip Memory for Data Bus
    • Avalon® Memory-Mapped Pipeline Bridge
  • Intel® Quartus® Prime software compiler settings. Intel uses the same Intel® Quartus® Prime design example for FMAX and Logic Size benchmark but with different compiler setup:
    • FMAX: superior_performance_optimized_placement_effort
    • Logic Size: area_aggressive
  • Toolchain:
    • Version Number:
      • xPack GNU RISC-V Embedded GCC, Linux 64-bit version: 10.1.1.0-1.1
      • CMake Version: 3.14.2
    • Compiler Configurations:
      • Compiler flags: -03
      • Assembler options: -Wa -gdwarf2
      • Compile options: -Wall -Wformat-security -march=rv32ia -mabi=ilp32
Disclaimer: Results may vary depending on the version of the Intel® Quartus® Prime software, the version of the Nios® V processor, compiler version, target device and the configuration of the processor. Additionally, any changes to the system logic design might change the performance and LE usage. All results are generated from design built with Platform Designer.