Nios® V Processor Reference Manual

ID 683632
Date 11/15/2021

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Document Table of Contents Hardware/Software Interface

Debug Module read or write to Debug Module registers, which initiate the interaction with the debugger. Each register has a fixed address as specified in the RISC-V Debug Support specification. Debugger can determine the register implementation status by write or read from the Debug Module registers. Unimplemented registers return 0 when read.

Debugger can check the status of the system by reading Debug Module Status (dmstatus) register. Debug Module Status register is read-only and provides status of the Debug Module and the selected harts.

You can access a specific hart by writing to the hartsel field in dmcontrol. Other fields in dmcontrol specify the action a debugger can take.

Halt Summary 0 (haltsum0) register reflects the status of a hart (halted/not halted). The LSB of this register can reflect whether hart is halted or not. Other bits is always 0. This is a read-only register of the debugger.

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