Nios® V Processor Reference Manual

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ID 683632
Date 11/15/2021
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Document Table of Contents
Document Table of Contents x
1. About this Document 2. Nios® V/m Processor 3. Document Revision History for the Nios® V Processor Reference Manual
1. About this Document x
1.1. Overview
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Control and Status Registers 2.3.4. Exception Controller 2.3.5. Interrupt Controller 2.3.6. Memory and I/O Organization 2.3.7. RISC-V based Debug Module
2.3.5. Interrupt Controller x
2.3.5.1. Timer and Software Interrupt Module
2.3.6. Memory and I/O Organization x
2.3.6.1. Instruction and Data Buses
2.3.6.1. Instruction and Data Buses x
2.3.6.1.1. Instruction Manager Port 2.3.6.1.2. Data Manager Port 2.3.6.1.3. Address Map
2.3.7. RISC-V based Debug Module x
2.3.7.1. Debug Mode 2.3.7.2. Halt from Debug Module 2.3.7.3. Debug Implementation 2.3.7.4. Abstract Commands in Debug Mode 2.3.7.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
1. About this Document
2. Nios® V/m Processor
3. Document Revision History for the Nios® V Processor Reference Manual

2.3.5. Interrupt Controller

The Nios® V/m processor implementation supports the following interrupts:
  • Platform interrupts with 16 level-sensitive interrupt request (IRQ) inputs.
  • Timer and Software interrupt - generated internally. You can access the timer interrupt register using the Timer and Software interrupt module interface by connecting to the data bus.

During an interrupt, the core writes the Program Counter of the attached instruction into the Machine Exception Program Counter (mepc) register. An interrupt is usually attached to the instruction in E-stage or in the preceding F or D pipeline stages. This is because the M-stage initiates the General Purpose Register. Thus, the core is not capable of retracting a memory instruction in M-stage. When an instruction in M-stage flags an exception while an interrupt is pending and ready to be serviced, the core will fetch and execute the exception instruction. If a memory or multicycle instruction is pending in M-stage, for example, the core is waiting for the response, the core does not flag an interrupt until the core receives a response for that instruction. Pending interrupts are flagged by their corresponding bits in Machine Interrupt-Pending (mip) register.

An interrupt is taken only when Machine Status Register (mstatus) bit 3 is asserted and bits corresponding to its pending interrupt in Machine Interrupt-pending (mip) register is asserted.

Table 7.  Interrupt Control and Status Registers/Bits
Register Description
mstatus mstatus[3] / Machine Interrupt-enable (MIE) field
  • Global interrupt-enable bit for machine mode
mie
mie[7] / Machine Timer Interrupt-enable (MTIE) field
  • Timer interrupt-enable bit for machine mode
mie[3] / Machine Software Interrupt-enable (MSIE) field
  • Software interrupt-enable bit for machine mode
mip mip[7] / Machine Timer Interrupt-pending (MTIP) field
  • Timer interrupt-pending bit for machine mode
mip[3] / Machine Software Interrupt-pending (MSIP) field
  • Software interrupt-pending bit for machine mode
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