Nios® V Processor Reference Manual

ID 683632
Date 11/15/2021

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2.4.2. Control and Status Registers (CSR) Mapping

Control and status registers report the status and change the behavior of the processor. Since the processor core only supports M-mode and D-mode, Nios® V/m processor implements the CSRs supported by these two modes.

Table 13.  Control and Status Registers List
Number Privilege Name Description
Machine Information Register
0xF11 MRO mvendorid Vendor ID. Refer to .
0xF12 MRO marchid Architecture ID. Refer to .
0xF13 MRO mimpid Implementation ID. Refer to .
0xF14 MRO mhartid Hardware thread ID. Refer to .
Machine Trap Setup
0x300 MRW mstatus Machine status register. Refer to .
0x301 MRW misa ISA and extensions. Refer to .
0x304 MRW mie Machine interrupt-enable register. Refer to .
0x305 MRW mtvec Machine trap-handler base address. Refer to .
Machine Trap Handling
0x341 MRW mepc Machine exception program counter. Refer to .
0x342 MRW mcause Machine trap cause. Refer to .
0x343 MRW mtval Machine bad address or instruction. Refer to .
0x344 MRW mip Machine interrupt pending. Refer to .
Debug Mode Registers
0x7B0 DRW dcsr Debug control and status register. Refer to .
0x7B1 DRW dpc Debug Program Counter. Refer to .