Nios® V Processor Reference Manual

Download PDF
ID 683632
Date 11/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About this Document 2. Nios® V/m Processor 3. Document Revision History for the Nios® V Processor Reference Manual
1. About this Document x
1.1. Overview
2. Nios® V/m Processor x
2.1. Processor Performance Benchmarks 2.2. Processor Pipeline 2.3. Processor Architecture 2.4. Programming Model 2.5. Core Implementation
2.3. Processor Architecture x
2.3.1. General Purpose Register File 2.3.2. Arithmetic Logic Unit 2.3.3. Control and Status Registers 2.3.4. Exception Controller 2.3.5. Interrupt Controller 2.3.6. Memory and I/O Organization 2.3.7. RISC-V based Debug Module
2.3.5. Interrupt Controller x
2.3.5.1. Timer and Software Interrupt Module
2.3.6. Memory and I/O Organization x
2.3.6.1. Instruction and Data Buses
2.3.6.1. Instruction and Data Buses x
2.3.6.1.1. Instruction Manager Port 2.3.6.1.2. Data Manager Port 2.3.6.1.3. Address Map
2.3.7. RISC-V based Debug Module x
2.3.7.1. Debug Mode 2.3.7.2. Halt from Debug Module 2.3.7.3. Debug Implementation 2.3.7.4. Abstract Commands in Debug Mode 2.3.7.5. Hardware/Software Interface
2.4. Programming Model x
2.4.1. Privilege Levels 2.4.2. Control and Status Registers (CSR) Mapping
2.4.1. Privilege Levels x
2.4.1.1. Machine Mode (M-mode) 2.4.1.2. Debug Mode (D-mode)
2.4.2. Control and Status Registers (CSR) Mapping x
2.4.2.1. Control and Status Register Field
2.5. Core Implementation x
2.5.1. Instruction Set Reference
1. About this Document
2. Nios® V/m Processor
3. Document Revision History for the Nios® V Processor Reference Manual

2.3.7.3. Debug Implementation

Assertion of haltreq bit send an asynchronous interrupt to the core logic. Core logic completes the instruction in W-stage. By the order of priority, instruction in M-stage, E-stage, D-stage or F-stage, takes the interrupt.
  • When there is a valid instruction in M-stage, the Program Counter writes to the Debug Program Counter.
  • If the instruction in M-stage is not valid, then instruction in E-stage can be interrupted and so on and so forth.
  • When there is no valid instruction in the pipe, the Program Counter for the next instruction to be executed writes to the Debug Program Counter.
For branches, the next Program Counter will depend on whether a branch was taken or not taken, and whether the prediction (if any) was correct or not.
Figure 3. Debug Module Block Diagram
Level Two Title