F-Tile Interlaken Intel® FPGA IP User Guide

Download PDF
ID 683622
Date 10/04/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About this IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About this IP Core x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Round-trip Latency 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multi-Segment Mode
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Example
4.2.2. Multi-Segment Mode x
4.2.2.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About this IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

5.2. Transmit User Interface Signals

Table 22.  Transmit User Interface SignalsThe input signals are synchronous to clk_tx_commom and output signals are synchronous to clk_rx_common.
Signal Name Width (Bits) I/O Direction Description
itx_chan 8 Input Transmit logic channel number for the first segment chunk. The IP core supports up to 256 channels. The IP core samples this value only when itx_sob is high and itx_num_valid has a non-zero value.
itx_chan1 8 Input Transmit logic channel number for the second segment chunk. The IP core supports up to 256 channels. DUAL or QUAD segment interface defines this signal. The IP core samples this value only when itx_sob is high and itx_num_valid has a non-zero value.
itx_num_valid Variable Input Indicates the number of valid 64-bit words in the current packet in the current data symbol. The width of the itx_num_valid depends on the parameter number of words and Number of segments

For single segment,

  • If number of words=4, then width=3 using itx_num_valid[2:0]
  • If number of words=8, then width=4 using itx_num_valid[7:4]
  • If number of words=16, then width=5 using itx_num_valid[9:5]
For multi-segment,
  • If number of words=8, then width=8 using itx_num_valid[7:4] (first segment chunk) and itx_num_valid[3:0] (second segment chunk)
  • If number of words=16, then width=10 using itx_num_valid[9:5] (first segment chunk) and itx_num_valid[4:0] (second segment chunk)
If number of words is equal to 8 and Number of segments is equal to 2:
  • itx_num_valid[7:4] indicates the number of valid words in itx_din_words[511:0]. The value can vary from 4’b0000 to 4’b1000.
  • itx_num_valid[3:0] indicates the number of valid words in itx_din_words[255:0]. The value can vary from 4’b0000 to 4'b0100.
In non-valid cycle, the value of itx_num_valid[7:4] and itx_num_valid[3:0] must be set to 4’b0000.

In the end of burst cycle (itx_eob=1), if the value of itx_num_valid[7:4] is equal to or less than 4'0100 and the parameter Number of Segments is set to 2 , then the value of itx_num_valid[3:0] can be set to values from 4'b0000 to 4'b0100. See the table below for valid values. If the value of itx_num_valid[3:0] is set to non-zero, you must set the value of itx_sob[0] to 1'b1.
itx_num_valid[7:4] itx_num_valid[3:0]
1, 2, 3, 4 0, 1, 2, 3, 4
5, 6, 7, 8 0
If number of words is equal to 8 and Number of segments is equal to 4:
  • itx_num_valid[7:4] indicates the number of valid words in itx_din_words[511:0]. The value can vary from 4’b0000 to 4’b1000.
  • itx_num_valid[3:0] indicates the number of valid words in itx_din_words[383:0]. The value can vary from 4’b0000 to 4’b0110.
In non-valid cycle, the value of itx_num_valid[7:4] and itx_num_valid[3:0] must be set to 4’b0000.
In the end of burst cycle (itx_eob=1), if the value of itx_num_valid[7:4] is equal to or less than 4'0110 and the parameter Number of segments is set to 4 , then the value of itx_num_valid[3:0] can be set to 4'b0000 to 4'b0110. See the table below for valid values. If the value of itx_num_valid[3:0] is set to non-zero, you must set the value of itx_sob[0] to 1'b1.
itx_num_valid[7:4] itx_num_valid[3:0]
1, 2 0, 1, 2, 3, 4, 5, 6
3, 4 0, 1, 2, 3, 4
5, 6 0, 1, 2
7, 8 0
If number of words is equal to 16 and Number of segments is equal to 2:
itx_num_valid[9:5] itx_num_valid[4:0]
1, 2, 3, 4, 5, 6, 7, 8 0, 1, 2, 3, 4, 5, 6, 7, 8
9, 10, 11, 12, 13, 14, 15, 16 0
If number of Words is equal to 16 and Number of segments is equal to 4:
itx_num_valid[9:5] itx_num_valid[4:0]
1, 2, 3, 4 0 to 12
5, 6, 7, 8 0 to 8
9, 10, 11, 12 0 to 4
13, 14, 15, 16 0
itx_eob 1 Input Indicates the current data symbol contains the end of the burst (EOB) for the first segment chunk.

This signal is used in SINGLE, DUAL or QUAD segment mode. When itx_eopbits has valid value of 4’b1xxx or 4’b0001, the itx_eob is valid too, but not vice-versa.

Whenever parameter TX_PKTMOD_ONLY is set to 0, you must provide this signal. Otherwise, when parameter TX_PKTMOD_ONLY is set to 1, the IP core ignores this signal. You are responsible to comply with the BurstMax and BurstMin setting.

itx_eob1 1 Input Indicates the current data symbol contains the end of the burst (EOB) for the second segment chunk.

This signal is used in DUAL or QUAD segment mode. When itx_eopbits1 has valid value of 4’b1xxx or 4’b0001, the itx_eob1 is valid too, but not vice-versa.

Whenever parameter TX_PKTMOD_ONLY is set to 0, you must provide this signal. Otherwise, when parameter TX_PKTMOD_ONLY is set to 1, the IP core ignores this signal. You are responsible to comply with the BurstMax and BurstMin setting.

itx_eopbits 4 Input Number of bytes at the end of packet for the first segment chunk. Indicates whether the current data symbol contains the end of a packet (EOP) with or without an error, and specifies the number of valid bytes in the current end-of-packet, non-error 8-byte data word, if relevant.
You must set the value of itx_eopbits as following:
  • 4b’0000: No end of packet, no error.
  • 4b’0001: Error and end of packet.
  • 4b’1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as following:
    • 000: all 8 bytes are valid.
    • 001: 1 byte is valid.
    • ...
    • 111: 7 bytes are valid.
All other values (4'b01xx, 4'b001x) are undefined. The valid bytes always start in bit positions [63:56] of the final valid data word of the packet.
itx_eopbits1 4 Input Number of bytes at the end of packet for the second segment chunk. Indicates whether the current data symbol contains the end of a packet (EOP) with or without an error, and specifies the number of valid bytes in the current end-of-packet, non-error 8-byte data word, if relevant.
You must set the value of itx_eopbits1 as following:
  • 4b’0000: no end of packet, no error.
  • 4b’0001: Error and end of packet.
  • 4b’1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as following:
    • 000: all 8 bytes are valid.
    • 001: 1 byte is valid.
    • ...
    • 111: 7 bytes are valid.
All other values (4'b01xx, 4'b001x) are undefined. The valid bytes always start in bit positions [63:56] of the final valid data word of the packet.
itx_sob Variable Input Indicates the current data symbol contains the start of a burst (SOB). If the IP core is in Interleaved mode, you are responsible for providing this start of the burst signal. If the IP core is in Packet mode, the IP core ignores this signal. The IP core samples the itx_chan signal during this cycle.
  • [1]— single segment
  • [1:0]—dual segment
  • [3:0]—four segment

{segment 3, segment 2, segment 1, segment 0} defines the segment order with segment 3 starts at the most significant bit location.

Using four segment as example, the signal has the following valid values:
  • [3]: indicates SOB for the first segment chunk.
  • [2:0]: only one bit can be set to indicate SOB for the second segment chunk.

For example:

If number of words= 16, Number of segments=4, tx_num_valid[9:5] =3, tx_num_valid[4:0]= 9, then the second segment starts at word[11], sob[3:0]= 4'1100

If number of words= 16, Number of segments=4, tx_num_valid[9:5] =9, tx_num_valid[4:0]= 4, then the second segment starts at word[3], sob[0]= 4'1001

itx_sop Variable Input Indicates the current data symbol on itx_din_words contains the start of a packet (SOP).
  • [1]— single segment
  • [1:0]—dual segment
  • [3:0]—four segment

{segment 3, segment 2, segment 1, segment 0} defines the segment order with segment 3 starts at the most significant bit location.

Using four segment as example, the signal has the following valid values:
  • [3]: indicates SOP for the first segment chunk.
  • [2:0]: only one bit can be set to indicate SOP for the second segment chunk.

For example:

If number of words, Number of segments=4, tx_num_valid[9:5] =3, tx_num_valid[4:0]= 9, then the second segment starts at word[11], sop[3:0]= 4'1100

If number of words= 16, Number of segments=4, tx_num_valid[9:5] =9, tx_num_valid[4:0]= 4, then the second segment starts at word[3], sop[0]= 4'1001

itx_din_words Variable Input The 64-bit words of input data (one data symbol). The width of the itx_dout_words depends on the parameter number of words.
  • If number of words=4, then width=256 bits.
  • If number of words=8, then width=512 bits.
  • If number of words=16, then width=1024 bits.

The first and last data word is in [511:448] and [63:0] respectively.

itx_calendar N * 16 Input Multiple pages (16 bits per page) of calendar input bits. The IP core copies these bits to the in-band flow control bits in N control words that it sends on the Interlaken link. N is the value of the Number of calendar pages parameter, which can be any of 1, 2, 4, 8. or 16. This signal is synchronous with tx_usr_clk, although it is not part of the user data transfer protocol.
itx_ready 1 Output Flow control signal to back pressure transmit traffic. When this signal is high, you can send traffic to the IP core. When this signal is low, you should stop sending traffic to the IP core within one to four cycles. You should provide itx_num_valid only after itx_ready is asserted.
Level Two Title