F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 10/04/2021

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1.4. Round-trip Latency

The following table includes the round-trip latency numbers for specific variants. The latency numbers were measured for the longest logical datapath for two highest lane rate and number of lanes variants, with FIFO level at 50 for the first packet.
Table 6.  Round-trip Latency Numbers
Device Number of Lanes Lane Rate (Gbps) Interlaken
Number of Segments Latency (Number of tx_usr_clk cycles)
F-tile (NRZ) 12 25.78125 4 271
F-tile (PAM4) 6 53.125 4 363