F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. About this IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About this IP Core x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Round-trip Latency 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multi-Segment Mode
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Example
4.2.2. Multi-Segment Mode x
4.2.2.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About this IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

1.3. Performance and Resource Utilization

This section covers the resources and expected performance numbers for selected variations of the Interlaken IP core using the Intel® Quartus® Prime Pro Edition software. Your results may slightly vary depending on the device you select.

For a comprehensive list of supported configurations, refer to Table 1. IP Supported Combinations of Number of Lanes and Data Rates

Table 4.  Resource Utilization for Interleaved ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 21.3.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ F-tile (NRZ) 4 6.25 24026 40064 7423 39
12 10.3125 64657 111490 19252 84
4 12.5 24037 39991 7620 39
8 44043 75390 13706 63
10 54170 93077 16681 72
12 64689 111450 19453 84
4 25.78125 24130 40134 8173 39
6 35640 62592 11541 63
8 44306 76093 14459 63
10 60421 108480 108480 111
12 70476 125196 21908 111
Intel® Agilex™ F-tile (PAM4) 6 53.125 68844 136667 24019 111
6 (with eFIFO) 69587 138310 23834 111
Table 5.  Resource Utilization for Packet ModeThe following numbers were obtained using the Intel® Quartus® Prime Pro Edition software version 21.3.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ F-tile (NRZ) 4 6.25 24034 39928 7503 39
12 10.3125 64720 111289 19457 84
4 12.5 24042 39662 7847 39
8 44082 75141 14012 63
10 54211 93088 16595 72
12 64706 111268 19684 84
4 25.78125 24206 40187 8172 39
6 35685 62214 11873 63
8 44303 75995 14677 63
10 60403 108569 18976 111
12 70469 125282 21706 111
Intel® Agilex™ F-tile (PAM4) 6 53.125 68871 136473 23992 111
6 (with eFIFO) 69562 138332 23623 111
Level Two Title