F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. About this IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About this IP Core x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Round-trip Latency 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multi-Segment Mode
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Example
4.2.2. Multi-Segment Mode x
4.2.2.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About this IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

5.1. Clock and Reset Interface Signals

Table 21.  Clock and Reset Interface Signals
Signal Name Width (Bits) I/O Direction Description
pll_ref_clk 1 Input F-tile reference clock source.

Connect to out_refclk_fgt_<n> output of F-Tile Reference and System PLL Clocks Intel FPGA IP core. For more information, refer to System PLL Configuration.

tx_pll_locked 1 Input Connects to the CSR block for status logging.
tx_usr_clk 1 Input Transmit side user data interface clock. The lower frequency of tx_usr_clk increases the latency of data path. You can also connect it to clk_tx_common.
rx_usr_clk 1 Input Receive side user data interface clock. The lower frequency of rx_usr_clk increases the latency of data path. You can also connect it to clk_rx_common.
clk_tx_common 1 Output Transmit PCS common lane clock driven by the SERDES transmit PLL.
clk_rx_common 1 Output Receive PCS common lane clock driven by CDR in transceiver.

The valid frequencies for clk_rx_common are same as clk_tx_common.

sysclk 1 Input This clock signal is only available in PAM4 IP core variations. Connect to out_systempll_clk_<m> output of F-Tile Reference and System PLL Clocks Intel FPGA IP core. For more information, refer to System PLL Configuration.
mac_clkin 1 Input This clock signal is only available in PAM4 IP core variations. This signal must be driven by a PLL and must use the same clock source that drives the pll_ref_clk.
reset_n 1 Input Active-low asynchronous reset signal for IP only. You must put the IP in reset when resetting the F-tile to prevent IP corruption while waiting for F-tile to be fully in reset.
tx_rst_n 1 Input Active low asynchronous reset for F-tile. This reset drives the tx_desired_state of SRC.
rx_rst_n 1 Input Active low asynchronous reset for F-tile. This reset drives the rx_desired_state of SRC. When you perform a Serial Internal Loopback CPI Command, this reset must be held low until TX is fully out-of-reset.
tx_rst_ack_n 1 Output Active low asynchronous reset acknowledge signal. Indicates that soft reset controller has successfully entered reset mode for TX side and you can now release the tx_rst_n signal. This signal stays low until you release the tx_rst_n signal.
rx_rst_ack_n 1 Output Active low asynchronous reset acknowledge signal. Indicates that soft reset controller has successfully entered reset mode for RX side and you can now release the rx_rst_n signal. This signal stays low until you release the rx_rst_n signal.
tx_usr_srst 1 Output Transmit-side reset output signal. Indicates the transmit side user data interface is under reset. This signal is synchronous with tx_usr_clk.
rx_usr_srst 1 Output Receive-side reset output signal. Indicates the receive side user data interface is under reset. This signal is synchronous with rx_usr_clk.
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