F-Tile Interlaken Intel® FPGA IP User Guide

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ID 683622
Date 10/04/2021
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Document Table of Contents
Document Table of Contents x
1. About this IP Core 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. IP Registers 7. F-Tile Interlaken Intel® FPGA IP User Guide Archives 8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide
1. About this IP Core x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Round-trip Latency 1.5. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Reference and System PLL Clock for your IP Design 2.5. Simulating the IP Core 2.6. Compiling the Full Design and Programming the FPGA
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode
2.4. Reference and System PLL Clock for your IP Design x
2.4.1. System PLL Configuration
4. Functional Description x
4.1. Data Path Flow 4.2. Modes of Operation 4.3. Performance 4.4. IP Reset 4.5. M20K ECC Support 4.6. Out-of-Band Flow Control
4.1. Data Path Flow x
4.1.1. Interlaken TX Path 4.1.2. Interlaken RX Path
4.1.1. Interlaken TX Path x
4.1.1.1. Transmit Path Blocks 4.1.1.2. In-Band Calendar Bits on Transmit Side
4.1.2. Interlaken RX Path x
4.1.2.1. Receive Path Blocks 4.1.2.2. In-Band Calendar Bits on Receive Side 4.1.2.3. RX Errored Packet Handling
4.1.2.3. RX Errored Packet Handling x
4.1.2.3.1. Example With Errors and In-Band Calendar Bits
4.2. Modes of Operation x
4.2.1. Interleaved and Packet Modes 4.2.2. Multi-Segment Mode
4.2.1. Interleaved and Packet Modes x
4.2.1.1. Transmit User Data Interface Examples 4.2.1.2. Receive User Data Interface Example
4.2.2. Multi-Segment Mode x
4.2.2.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals
1. About this IP Core
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. IP Registers
7. F-Tile Interlaken Intel® FPGA IP User Guide Archives
8. Document Revision History for F-Tile Interlaken Intel® FPGA IP User Guide

5.6. Interlaken Link and Miscellaneous Signals

Table 27.  SERDES Pins
Signal Name Width (Bits) I/O Direction Description
tx_pin Number of lanes Output Each bit represents the differential pair on a TX Interlaken lane.
rx_pin Number of lanes Input Each bit represents the differential pair on a RX Interlaken lane.
tx_pin_n Number of lanes Output For the PAM4 loopback example design, tx_pin_n drives data to rx_pin_n.
rx_pin_n Number of lanes Input For the PAM4 loopback example design, rx_pin_n receives data from tx_pin_n.
Table 28.  Real-Time Transmitter Status Signals
Signal Name 2 Width (Bits) I/O Direction Description
tx_lanes_aligned 1 Output Indicates whether all of the transmitter lanes are aligned and are ready to send traffic.
itx_overflow 1 Output An error flag indicating that the Transmit buffer is currently overflowing. This signal is asserted for the duration of the overflow condition. It is asserted in the first clock cycle in which the overflow occurs, and remains asserted until the Transmit buffer pointers indicate that no overflow condition exists.
itx_underflow 1 Output An error flag indicating that the Transmit buffer is currently underflowed. In normal operation, this signal may be asserted temporarily immediately after the Interlaken IP core comes out of reset.
Table 29.  Real-Time Receiver Status Signals
Signal Name 3 Width (Bits) I/O Direction Description
rx_lanes_aligned 1 Output Indicates whether all of the receiver lanes are aligned and are ready to receive traffic.
sync_locked Number of lanes Output Receive lane has locked on the remote transmitter meta Frame. These signals are level signals: all bits are expected to stay high unless a problem occurs on the serial line.
word_locked Number of lanes Output Receive lane has identified the 67-bit word boundaries in the serial stream. These signals are level signals: all bits are expected to stay high unless a problem occurs on the serial line.
crc24_err 1 Output A CRC24 error flag covering both control word and data word. You can use this signal to count the number of CRC24 errors. This signal is asserted as a single cycle wide pulse.
crc32_err Number of lanes Output An error flag indicating diagnostic CRC32 failures per lane. This signal is asserted as a single cycle wide pulse only for NRZ mode.
irx_overflow 0 Output This signal is tied to 0 and it is not used.
rdc_overflow 0 Output This signal is tied to 0 and it is not used.
rg_overflow 1 Output An error flag indicating that the Reassembly FIFO is currently overflowed. The Reassembly FIFO is the receiver FIFO that feeds directly to the user data interface.
sop_cntr_inc 1 Output A pulse indicating that the IP core receiver user data interface received a start-of- packet (SOP). You can use this signal to increment a count of SOPs the application observes on the receive interface.
eop_cntr_inc 1 Output A pulse indicating that the IP core receiver user data interface received an end-of-packet (EOP). You can use this signal to increment a count of EOPs the application observes on the receive interface.
sop_cntr_inc1   Output A pulse indicating that the IP core receiver user data interface received a start-of- packet (SOP) on second segment chunk. You can use this signal to increment a count of SOPs the application observes on the receive interface.

This signal is only available in muti-segment mode of IP core variations.

eop_cntr_inc1   Output A pulse indicating that the IP core receiver user data interface received an end-of-packet (EOP) on second segment chunk. You can use this signal to increment a count of EOPs the application observes on the receive interface.

This signal is only available in muti-segment mode of IP core variations.

rxfifo_fill_ level RXFIFO_ADDR_ WIDTH Output The fill level of the Reassembly FIFO, in units of 64-bit words. The width of this signal is the value of the RXFIFO_ADDR_WIDTH parameter, which is 12 by default. You can use this signal to monitor when the RX Reassembly FIFO is empty.
rx_xcoder_uncor_feccw [XCODER_LANES-1:0]] Output Indicates uncorrectable FEC code word. This signal is also accessible through status register and may not align with the irx_data signal.

This signal is only available in PAM4 IP core variations.

Table 30.  Burst Control Settings
Signal Name Width (Bits) I/O Direction Description
burst_max_in 4 Input Encodes the BurstMax parameter for the IP core. The actual value of the BurstMax parameter must be a multiple of 64 bytes. While traffic is present, this input signal should remain static. However, when no traffic is present, you can modify the value of the burst_ max_in signal to modify the BurstMax value of the IP core. The IP core supports the following valid values for this signal:
  • 4'b0010: 128 bytes
  • 4'b0100: 256 bytes
  • 4'b1000: 512 bytes4
burst_short_in 4 Input Encodes the BurstShort parameter for the IP core. The IP core supports the following valid value for this parameter:
  • 4'b0001: 32 bytes
  • 4'b0010: 64 bytes
In general, the presence of the BurstMin parameter makes the BurstShort parameter obsolete.
burst_min_in 4 Input Encodes the BurstMin parameter for the IP core. The IP core supports the following valid values for this signal:
  • 4'b0000: Disable optional enhanced scheduling. If you disable enhanced scheduling, performance is non-optimal.
  • 4'b0001: 32 bytes5
  • 4'b0010: 64 bytes
  • 4'b0100: 128 bytes
The BurstMin parameter should have a value that is less than or equal to half of the value of the BurstMax parameter.

Intel® recommends that you modify the value of this input signal only when no traffic is present on the TX user data interface. You do not need to reset the IP core.

Table 31.  ECC Status Signals
Signal Name Width (Bits) I/O Direction Description
itx_eccstatus 2 Output Indicates the TX ECC status.
  • Bit 1: Correctable error status
  • Bit 0: Uncorrectable error status
irx_eccstatus 2 Output Indicates the RX ECC status.
  • Bit 1: Correctable error status
  • Bit 0: Uncorrectable error status
2 Synchronous with tx_usr_clk.
3 Synchronous with rx_usr_clk.
4 This value is not supported for number of words=4.
5 This value is not supported for number of words= 8 and number of words= 16 .
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