1. About this IP Core
|Intel® Quartus® Prime Design Suite 21.3|
|IP Version 3.0.0|
Interlaken is a high-speed serial communication protocol for chip-to-chip packet transfers. The F-Tile Interlaken Intel® FPGA IP core implements the Interlaken Protocol Specification, v1.2. The F-Tile Interlaken Intel® FPGA IP core supports multiple combinations of number of lanes (4 to 12) and lane rates from 6.25 gigabits per second (Gbps) to 53.125 Gbps providing raw bandwidth up to 300 Gbps.
Interlaken provides low I/O count compared to earlier protocols, supporting scalability in both number of lanes and lane speed. Other key features include flow control, low overhead framing, and extensive integrity checking. The Interlaken IP incorporates a physical coding sublayer (PCS), a physical media attachment (PMA), and a media access control (MAC) block.